$115.91/hr

Hybrid

Full-time

Siemens DFT tools

Streaming Scan Network (SSN)

Scan compression and insertion

Memory BIST and repair scheme implementation

Logic BIST

JTAG/IJTAG

At-speed test

ATPG

Fault simulation

DFT mode timing constraints

Back-annotated gate level verification

Silicon debug

Memory and scan diagnostics

2.5D and 3D test

Verilog RTL

TCL

Perl

SoC architectures

Multi-clock domain design

Low power design

Arm IP

Cortex CPUs

Mali GPUs

AMBA protocols

CoreLink interconnects

CoreSight debug

High performance design

Implementation

Timing convergence

Datacenter SOCs

Cadence DFT tools

Synopsys DFT tools

Simulation tools