Lead DFT design and STA constraints to meet design PPA targets. Coordinates DFT requirements across SOC, IP and product teams. Architect, implement, and validate innovative DFT techniques on SOCs and sub-systems. Insert DFT logic into SoC as well as sub-system level and validate all DFT features using industry standard simulation tools. Work closely with multi-functional teams to support DFT RTL level insertion, synthesis and scan insertion, place-and-route, and static-timing-analysis and timing...

Skills