'%3e%3cpath%20fill-rule='evenodd'%20clip-rule='evenodd'%20d='M6.51571%2013.3023L9.79848%2019.4985V19.4911H15.6622L11.6387%2012.9597C14.9215%2012.4682%2017.3075%209.87651%2017.9547%206.9199C18.3914%204.92401%2018.0093%202.9579%2016.6291%201.6844C15.1866%200.358772%2012.8629%200.306641%2010.742%200.306641H4.38698L0.191895%2019.4985H5.10436L6.46113%2013.3023H6.51571ZM8.36374%204.61122H10.2351C11.9974%204.61122%2013.3932%205.31127%2012.9799%207.2029C12.551%209.17645%2010.9369%209.95098%209.01093%209.95098H7.1941L8.36374%204.61122Z'%20fill='%2318181B'/%3e%3cpath%20d='M87.8598%2017.726C87.8598%2018.7049%2087.0289%2019.4985%2086.004%2019.4985C84.9791%2019.4985%2084.1482%2018.7049%2084.1482%2017.726C84.1482%2016.7471%2084.9791%2015.9536%2086.004%2015.9536C87.0289%2015.9536%2087.8598%2016.7471%2087.8598%2017.726Z'%20fill='%2318181B'/%3e%3cpath%20fill-rule='evenodd'%20clip-rule='evenodd'%20d='M23.7717%2019.9379C19.1556%2019.9379%2016.364%2016.6983%2017.3309%2012.2895C18.29%207.88061%2022.5007%204.64101%2027.1169%204.64101C31.733%204.64101%2034.5245%207.88061%2033.5577%2012.2895C32.5985%2016.6983%2028.3801%2019.9379%2023.7717%2019.9379ZM26.2357%208.65514C24.146%208.65514%2022.259%2010.3382%2021.8301%2012.282C21.4013%2014.2258%2022.5553%2015.9089%2024.645%2015.9089C26.7348%2015.9089%2028.6218%2014.2258%2029.0507%2012.282C29.4795%2010.3457%2028.3255%208.65514%2026.2357%208.65514Z'%20fill='%2318181B'/%3e%3cpath%20fill-rule='evenodd'%20clip-rule='evenodd'%20d='M45.1916%2017.942L44.8485%2019.4985H49.1293L53.3322%200.3141H48.8252L47.5075%206.33157C46.5484%205.13999%2045.1994%204.61868%2043.4605%204.61868C38.9301%204.61868%2035.2341%208.08915%2034.3218%2012.2671C33.3939%2016.5196%2035.5694%2019.9677%2040.1855%2019.9677C41.9556%2019.9677%2043.8504%2019.4687%2045.137%2017.942H45.1916ZM38.8366%2012.2373C39.2966%2010.1372%2041.2772%208.63281%2043.4527%208.63281C45.6282%208.63281%2046.9226%2010.1595%2046.4626%2012.2373C46.0025%2014.3673%2044.0531%2015.9461%2041.7996%2015.9461C39.5462%2015.9461%2038.3765%2014.3375%2038.8366%2012.2373Z'%20fill='%2318181B'/%3e%3cpath%20fill-rule='evenodd'%20clip-rule='evenodd'%20d='M66.9857%2013.6076H55.6949C55.5935%2015.3205%2056.8645%2016.3334%2058.6268%2016.3334C59.851%2016.3334%2060.7399%2015.8642%2061.66%2014.9854H66.2762C64.3424%2017.8601%2061.2234%2019.9602%2057.8314%2019.9602C53.4336%2019.9602%2050.6031%2016.5344%2051.5232%2012.3341C52.4355%208.15616%2056.693%204.61121%2061.1142%204.61121C65.7303%204.61121%2068.2957%208.14126%2067.3444%2012.4682C67.2587%2012.8554%2067.1495%2013.2204%2066.9857%2013.6076ZM60.3422%208.24552C58.7125%208.24552%2057.0751%209.1541%2056.3811%2010.7106H63.2195C63.2117%209.14665%2061.9719%208.24552%2060.3422%208.24552Z'%20fill='%2318181B'/%3e%3cpath%20fill-rule='evenodd'%20clip-rule='evenodd'%20d='M68.093%2012.2895C67.1261%2016.6983%2069.9176%2019.9379%2074.5338%2019.9379C79.15%2019.9379%2083.3606%2016.6983%2084.3275%2012.2895C85.2944%207.88061%2082.5029%204.64101%2077.8867%204.64101C73.2706%204.64101%2069.0599%207.88061%2068.093%2012.2895ZM72.6%2012.282C73.0289%2010.3382%2074.9159%208.65514%2077.0056%208.65514C79.0954%208.65514%2080.2416%2010.3457%2079.8205%2012.282C79.3917%2014.2258%2077.5047%2015.9089%2075.4149%2015.9089C73.3252%2015.9089%2072.1711%2014.2258%2072.6%2012.282Z'%20fill='%2318181B'/%3e%3c/g%3e%3cdefs%3e%3cclipPath%20id='clip0_3016_7209'%3e%3crect%20width='88'%20height='20'%20fill='white'/%3e%3c/clipPath%3e%3c/defs%3e%3c/svg%3e)
Staff Engineer - Design
Arm
Austin
Early applicant
Hybrid
Full-time
The candidate will join the System IP Coherent Interconnect design team responsible for the development of several innovative and powerful AMBA based IPs for the Infrastructure, IoT, and Automotive line of business.
The candidate should have a detailed understanding across all design aspects to deliver successful IP with optimal PPA. This includes low-power design techniques and the awareness of the impact of design decisions on system performance. In addition, the candidate would fully apply...
Skills
Micro-architecture
Logic design
SystemVerilog
RTL coding
AMBA CHI
AXI
PCI Express
Ethernet
DDR
Transaction ordering
Virtualization
MMUs
Cache coherence
Host bridge functions
Synthesis
Static timing
DFT
Physical design
Verification methods
Perl
Ruby
Unix/Linux
Makefiles
Communication
Collaboration
Presentation skills
Staff Engineer - Design
Arm
Austin
Early applicant
Hybrid
Full-time
The candidate will join the System IP Coherent Interconnect design team responsible for the development of several innovative and powerful AMBA based IPs for the Infrastructure, IoT, and Automotive line of business.
The candidate should have a detailed understanding across all design aspects to deliver successful IP with optimal PPA. This includes low-power design techniques and the awareness of the impact of design decisions on system performance. In addition, the candidate would fully apply...
Skills
Micro-architecture
Logic design
SystemVerilog
RTL coding
AMBA CHI
AXI
PCI Express
Ethernet
DDR
Transaction ordering
Virtualization
MMUs
Cache coherence
Host bridge functions
Synthesis
Static timing
DFT
Physical design
Verification methods
Perl
Ruby
Unix/Linux
Makefiles
Communication
Collaboration
Presentation skills