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Kandou AI

Analog Design Engineer

Reading
Posted about 20 hours ago
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About Kandou

At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.

Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.

Kandou’s architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future.

Job Title: Analog Design Engineer

Location: EU/CH/UK

Key Responsibilities

  • Position in design, modeling, and verification of custom analog designs for high-speed Serdes transceivers in advanced technology nodes
  • Design and verification of analog circuits, following prescribed design and documentation flows, to meet architecture specifications
  • If necessary, support and interact with customers on requirements, design specifications, performance results, and product delivery
  • Support analog IP and chip level integration
  • Collaborate with architects, technical leads, analog and digital design, layout, integration, verification, silicon validation, and quality teams as needed

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Graduate Consultant — 2026 Scheme

PwC·London, UK
£35,000/yr

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You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.

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Competencies

  • Skilled in the design of high-speed analog Serdes circuits including DFT, DFM, and ESD protection, with a deep knowledge of transistor and wireline communications fundamentals
  • Understanding of layout approaches and design techniques used for high-speed and high-precision circuits
  • Advanced user of EDA tools for design and verification of analog circuits, preferably using the Cadence Virtuoso environment, including their use for simulation, parasitic extraction, electromagnetic modelling, EM/IR, and reliability analysis as well as LVS and DRC
  • Self-motivated, a strong sense of ownership and responsibility with good verbal and written communication skills and a team player
  • Ability to manage and complete designs to schedule using defined design process flows as well as reporting design status to internal management team

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Requirements

  • The candidate should have a Master's or Ph.D. degree in Electronics or other relevant fields
  • Minimum 5 years of experience in analog design and layout of key circuits in multi-gigabit serial data-link transceivers or RF multi-tone communications such as equalizers, clock generators, clock and data recovery circuits, TISAR ADC’s, serialisers, and output drivers, etc.
  • Expertise in design and layout of high-speed circuits such as oscillators, phase-locked loops, delay-locked loops, and other fundamental building blocks like biasing, amplifiers, buffers, regulators, filters, ADC, DAC, etc.
  • Experience with modern semiconductor process technologies, preferably in finFet technology nodes
  • Experience using Ocean, MDL, or equivalent to automate analog design verification is highly desirable

If this is the role you have been looking for and want to be part of a growing company with an exciting future, we would really love to hear from you. Together We Kandou It!

Visit us at www.kandou.ai and https://www.linkedin.com/company/kandou-ai/

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Location

Reading, England, United Kingdom

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