Senior Digital ASIC Design Engineer - Hammersmith

An innovative semiconductor startup developing advanced ASIC technology for next generation medical and neurotechnology applications is looking for a Senior Digital ASIC Design Engineer. Their work combines ultra low power digital design with analogue and mixed signal technology, creating highly integrated solutions for demanding applications.

They are looking for a Senior Digital Design Engineer to take ownership of the front end digital development of their ASICs. This is a hands on role covering architecture, RTL design, verification and supporting the design through to silicon.

As a Senior Digital Design Engineer, you will:

• Own the architecture and RTL development of digital control, communication and power management functionality
• Develop clean, synthesizable Verilog/SystemVerilog for low power mixed signal ASICs
• Build and maintain SystemVerilog verification environments, including assertions, coverage and self checking testbenches
• Work closely with analogue and system engineers to define interfaces, registers, clocks and calibration functionality
• Take designs through lint, CDC/RDC, synthesis and timing analysis, working closely with Physical Design where required
• Support FPGA based prototyping, pre silicon validation and eventual silicon bring up
• Contribute to design reviews, technical documentation and verification planning