Yoh, A Day & Zimmermann Company
Application Specific Integrated Circuit Design Engineer
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Digital Hardware Design Engineers
Mid, Senior, Principal & Technical Lead levels
Cambridge | Hybrid working
A new digital hardware team is being built in Cambridge.
Not an extension of an established department where every technical decision has already been made. A new engineering hub where the first hires will help shape the team, its working practices and how complex FPGA and ASIC products are delivered.
The company develops hardware-accelerated Layer 1 technology for 5G and satellite communications. Its IP is being developed for use within space-based communications systems, creating new engineering challenges around throughput, latency, power consumption and efficient use of hardware resources.
We are looking for digital design engineers at several levels, from experienced individual contributors through to principal engineers and technical leads.
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You will work with algorithm and system architecture teams to turn communications requirements into practical microarchitectures and RTL implementations. The work covers the wider development cycle, including FPGA and ASIC design, simulation, testbench creation, synthesis, timing closure, optimisation, hardware deployment and system integration.
The core experience
- Verilog or SystemVerilog RTL design for complex FPGA or ASIC products
- Delivery of digital hardware through implementation, simulation and synthesis
- Timing, power and resource optimisation for high-throughput systems
- Collaboration across architecture, design, verification and implementation teams
Depending on your level, you may also contribute to technical direction, mentor other engineers, improve development methodology or lead the delivery of larger pieces of IP.
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Experience in communications signal processing, modems, DSP, AMBA protocols, UVM, SystemC, PCIe, JESD or AMD FPGA platforms would be useful, but direct wireless experience is not essential.
What matters more is an understanding of how to take a demanding technical requirement and turn it into hardware that meets its performance, power and implementation constraints.
The technology already exists. The commercial demand is creating the need to scale it.
For the engineers joining the Cambridge team, that means an opportunity to influence what is built, how it is implemented and how the new engineering group develops.
To discuss the roles confidentially, contact Tom Bird at Yoh.
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