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Application Specific Integrated Circuit Design Engineer

London
Posted about 16 hours ago
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Senior ASIC Design Engineer – AI Accelerators - London

An exciting opportunity has arisen for an ASIC Design Engineer to join a well-funded semiconductor start-up developing next-generation AI accelerator technology. Whilst there is no strict experience level - this role would suit someone best with between 4-7 years experience.

The company is taking a different approach to AI computing, developing highly configurable, bespoke accelerator architectures designed to overcome the inefficiencies of traditional GPU and NPU solutions.

With impressive early performance results and backing from established investors in the semiconductor industry, including a co-founder of Arm, the business is now looking to expand its engineering team.

This is an opportunity to join a small, highly technical team where you'll have genuine influence over the architecture, contribute to key design decisions and take ownership of RTL development from initial specification through to implementation.

The Role

  • Design and develop RTL for high-performance AI accelerator architectures.
  • Contribute to architectural decisions and the wider technical roadmap.
  • Optimise existing designs for power, performance and area (PPA).
  • Take designs through the full development lifecycle, from specification to integration.
  • Work closely with verification and software teams.
  • Support the integration of accelerator IP into complex SoC environments.
  • Identify opportunities to improve performance and efficiency across the architecture.

Reasons to use Rodeo

I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?

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Graduate Consultant — 2026 Scheme

PwC·London, UK
£35,000/yr

Why you're a good match

Strong

Your economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.

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Why you're a good match

You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.

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Strong

Experience fit

Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.

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Experience Required

  • Strong RTL design experience using Verilog/SystemVerilog.
  • Experience in ASIC and/or FPGA design and development.
  • Previous experience taking designs through to silicon.
  • Understanding of processor architectures, SoC design or accelerator development.
  • Experience with PPA optimisation.
  • Knowledge of scripting languages such as Python or Tcl.

Experience in any of the following would also be beneficial:

  • AI/ML accelerator architectures and workloads.
  • Digital Signal Processing (DSP).
  • Arm or RISC-V based systems.
  • FPGA platforms including AMD, Altera or Lattice.
  • Verification tools such as Cocotb or Verilator.

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The appeal of this opportunity is the level of technical involvement and ownership available. Rather than working on a small part of a much larger design, you'll have the chance to contribute across the architecture and see your work progress into customer applications. The company is still at an exciting stage of its development, with a strong technical team, experienced investors and ambitious plans for its AI accelerator technology. For engineers who enjoy architecture, RTL development and solving challenging design problems, this offers an opportunity to work on something different from traditional semiconductor development.

If you're interested in finding out more, please get in touch for a confidential discussion.

You must have full UK working rights to be considered for the role.

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Location

London, England, United Kingdom

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