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Application Specific Integrated Circuit Design Engineer
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Title: ASICS Engineering
Contract: Sept 28, 2026 – Dec 23, 2026
Hours per Week: 37 hours
Location: Farnborough, UK
TECHNICAL SKILLS
Must Have
- Analogue Layout
- Cadence
- CMOS IC Design
- Spectre
JOB DESCRIPTION:
Experience Required: 4-8 years
The senior engineer will take on the design of multiple analogue blocks including LDOs, temperature sensors, central biasing, test bus and process monitors. The tasks will include:
- Review of block specifications and architecture selection.
- Schematic design, simulation and reporting compliance to specifications.
- Overseeing a layout engineer to complete the layout.
- Post-layout parasitic simulation and necessary adjustments.
- Documentation of usage and any calibrations etc.
- Liaising with the chip lead to integrate the designs.
- Presentation of design for block-level reviews.
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Key Responsibilities:
- Acts as a key contributor in a complex environment.
- Responsible for the delivering the fully verified blocks.
- Solves complex problems in a tightly constrained environment.
- Fully competent in Analogue design for complex sub-cells and small subsystems.
- Keeps abreast of new developments and is technical expert in the design of analogue sub-cells.
- Ensures quality of the solution; works with macro lead to ensure timely delivery of subsystems.
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