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Redline UK

ASIC Architect

Oxford
Posted 1 day ago
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Great opportunity for an experienced ASIC Architect to join an innovative next-generation computing company and take ownership of the architecture and development of a cutting-edge probabilistic computing processor. This is a highly influential role where you will lead ASIC architecture from algorithm and ISA definition through to tape-out and silicon bring-up.

Key Responsibilities for the ASIC Architect role based in Oxford:

  • Own the end-to-end ASIC architecture of a probabilistic computing processor, from algorithm understanding through to tape-out.
  • Define system architecture, instruction set architecture (ISA) and dataflow models based on workload requirements.
  • Perform HW/SW co-design activities, including arithmetic implementation and analysis of programmability and host requirements.
  • Build functional simulations and performance models to guide architectural decisions.
  • Conduct timing, power and area trade-off analysis with strong physical design awareness.
  • Define detailed microarchitecture specifications, including memory hierarchy, connectivity and interface requirements.
  • Lead internal IP development and evaluate third-party IP solutions.
  • Guide designs through verification, sign-off, tape-out and silicon bring-up.

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Graduate Consultant — 2026 Scheme

PwC·London, UK
£35,000/yr

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Your economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.

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Why you're a good match

You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.

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Key Skills Required for the ASIC Architect role based in Oxford:

  • Proven architectural ownership of at least one ASIC taken successfully to tape-out, ideally within compute accelerators, inference engines or DSP applications.
  • Strong hands-on experience with performance modelling, simulation and architectural trade-off analysis using Python, C++ or similar languages.
  • Experience with industry-standard semiconductor tool flows such as Synopsys, Cadence or Siemens EDA tools.
  • Solid understanding of timing, power and area optimisation at the architectural level.
  • Experience defining hardware/software interfaces and collaborating with firmware and compiler teams.
  • Strong RTL design knowledge and experience defining verification strategies from an architectural perspective.

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This is a fantastic opportunity to play a pivotal role in developing revolutionary computing technology, influencing product direction and driving innovation from concept through to silicon deployment.

APPLY NOW! To apply for this ASIC Architect opportunity located in Oxford, please send your CV to, or for more information contact Mike Belmar on 01582 878807.

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Skills

ASIC Architecture
Instruction Set Architecture (ISA)
HW/SW Co-design
Performance Modelling
Python
C++
Synopsys
Cadence
Siemens EDA
RTL Design
Physical Design Awareness
Microarchitecture Specification
Verification Strategies
Silicon Bring-up
Tape-out

Location

Oxford, England, United Kingdom

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