IC Resources
ASIC Design Engineer

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ASIC Design Engineer (Senior/Staff/Principal levels)
This is a fantastic opportunity to join a start-up who are just over 2 years old, as they make technological breakthroughs in security with a product line built on CHERI technology and RISC‑V cores.
They have strong funding behind them and a leadership team made up of experts in processor design and formal methods as well as a CEO who brings over 30 years of semiconductor experience from world renown companies and start-ups. With huge growth plans across the Silicon Design team this is a fantastic time to join the business!
I am seeking an Engineer who has experience in the full ASIC flow.
Ideally you will have experience in end-to-end ASIC development, from RTL through to GDSII, including synthesis, DFT, floorplanning, place and route, static timing analysis, and tapeout support. This is a hands-on technical role, ideal for someone with a deep understanding of digital design and physical implementation, and a passion for building cutting-edge silicon.
Reasons to use Rodeo
I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?
Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.
Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.
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Graduate Consultant — 2026 Scheme
Why you're a good match
StrongYour economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.
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Why you're a good match
You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.
Experience fit
Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.
Only hits
No noise. No "maybe this fits." Just roles with a clear explanation of why they're right — and where to focus when applying.
Responsibilities
- Collaborates with cross-functional teams to define and implement ASIC architectures
- Designs and develops RTL code using SystemVerilog and Verilog
- Conducts design verification and ensures compliance with specifications
- Participates in the integration and testing of ASICs
- Contributes to the improvement of design methodologies and processes
- Integrate IPs, define constraints, and ensure timing, area, and power goals are met
- Work closely with RTL, verification, and DFT teams to ensure robust handoffs and convergence
Qualifications
- Holds a Bachelor’s or Master’s degree in Electrical Engineering or related field
- Demonstrates a solid understanding of ASIC design principles and methodologies
- Proficient in SystemVerilog, Verilog, and RTL Design
- Possesses familiarity with security-related applications and protocols, which is a plus
- Exhibits strong problem-solving skills and attention to detail


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Day-to-day
- Collaborating with other engineers and cross-functional teams to define project requirements
- Writing RTL code and conducting design verification
- Participating in design reviews and providing input to improve ASIC design methodologies
- Contributing to the development of innovative solutions in the field of security
UK Based Start-Up
Offering company share options and a competitive base.
Location
Cambridge or UK Remote: You must be currently living and working in the UK and able to do so without restrictions.
For more information, please contact Rachel Mason at IC Resources.
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