Oliver Bernard
C++ Team Lead (Low Latency)
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C++ Low-Latency Technology Lead
Location: London — 3 days per week in the office
Salary: £200,000 + 25% bonus
We’re looking for an exceptional C++ Low-Latency Technology Lead to join a high-performance technology team within a leading financial services firm.
This is a hands-on technical leadership role for someone who is passionate about ultra-low-latency systems, performance engineering and modern C++, and who can lead engineers while remaining deeply involved in the architecture and optimisation of critical trading technology.
The Role
- You’ll take technical ownership of a highly performance-sensitive C++ platform, driving improvements across architecture, latency, throughput and reliability.
- You’ll work closely with developers, quantitative teams and senior technology stakeholders to solve some of the hardest performance challenges in financial technology.
What You’ll Bring
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- Extensive commercial experience developing high-performance C++ systems
- Strong expertise in low-latency / ultra-low-latency technology
- Deep understanding of C++ performance optimisation, memory management and CPU architecture
- Proven experience with garbage collection tuning and JVM performance, particularly where C++ and Java systems interact
- Strong knowledge of concurrency, multithreading, lock-free programming and cache-aware design
- Experience profiling and eliminating latency at microsecond and sub-microsecond levels
- Excellent understanding of Linux, networking and systems-level performance
- Experience leading technically demanding engineering projects and mentoring senior engineers
- Strong communication skills, with the ability to influence architecture and technical strategy
Desirable
- Experience within trading, capital markets, electronic trading or financial technology
- Experience with market data, order management or execution systems
- Knowledge of kernel/network optimisation, CPU affinity, NUMA and hardware-level performance
- Experience with performance tooling, benchmarking and latency analysis
- Familiarity with FPGA or hardware acceleration
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Why Join?
- £200,000 base salary
- 25% annual bonus
- Senior technical leadership position with significant ownership
- Highly performance-focused engineering environment
- Opportunity to work on genuinely challenging, latency-critical systems
- London-based, 3 days per week in the office
If you’re a senior C++ engineer or technology lead who thrives on squeezing every last microsecond out of complex systems, this is an opportunity to make a significant impact at the heart of a high-performance financial technology environment.
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