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CPU Architect, Hardware

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CPU Architect, Hardware
Location: Cambridge, UK
Type: Contractor
Headcount: 1
Experience: 4+ years
Visa: Visa sponsorship is not available for this contractor position.
About the Role
Our client is looking for a CPU Hardware Architect to contribute to the development of a new and competitive CPU architecture.
You will help define the interfaces between CPU hardware, firmware and operating systems while collaborating with other architects to translate product and system requirements into architectural solutions.
Key Responsibilities
- Contribute to the definition and development of next-generation CPU architecture.
- Define interfaces between hardware, firmware and operating systems.
- Work with CPU architects and engineering teams on architectural specifications.
- Translate system and user requirements into practical CPU architecture solutions.
- Support modelling and analysis of processor architectures.
- Contribute to hardware/software co-design activities.
Reasons to use Rodeo
I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?
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Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.
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Graduate Consultant — 2026 Scheme
Why you're a good match
StrongYour economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.
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Why you're a good match
You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.
Experience fit
Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.
Only hits
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Requirements
- 4+ years of relevant CPU architecture or microarchitecture experience.
- Strong understanding of CPU Instruction Set Architecture and assembly language.
- Knowledge of Arm, RISC-V and/or MIPS architecture.
- Understanding of modern CPU core microarchitecture.
- Software development experience using C, C++, assembly and/or Python.
- Experience modelling microprocessors using high-level languages such as C/C++.
- Comfortable working within geographically distributed engineering teams.


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Desirable
Experience with one or more of the following would be particularly valuable:
- Advanced Vector Extensions (AVX)
- Scalable Vector Extension (SVE)
- Scalable Matrix Extension (SME)
- Confidential Compute Architecture (CCA)
- Morello / CHERI
- Compiler backend development
- Code generation
- Performance analysis and optimisation
An MS or PhD in Electrical Engineering, Computer Science or a related field would also be advantageous.
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