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CPU Hardware Architect – CPU Architecture & Microarchitecture | CPU Architecture / ISA / Arm / RISC-V / MIPS / Hardware-Software Co-Design
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CPU Hardware Architect – CPU Architecture / ISA / Arm / RISC-V / MIPS / Hardware-Software Co-Design
We are currently partnered with a global technology organisation with a major R&D presence in Cambridge, supporting the development of a new and competitive CPU architecture. They are looking for a CPU Hardware Architect to contribute to architectural definition, hardware/software interfaces, and processor design. You will work closely with CPU architects and engineering teams to translate product and system requirements into practical architectural solutions, while helping define interfaces between CPU hardware, firmware, and operating systems.
Key Responsibilities
- Contribute to the definition and development of next-generation CPU architectures.
- Define and refine interfaces between CPU hardware, firmware, and operating systems.
- Work closely with CPU architects and engineering teams to develop architectural specifications.
- Translate system, product, and user requirements into practical CPU architecture solutions.
- Support processor architecture modelling, analysis, and evaluation.
- Contribute to hardware/software co-design and optimisation activities.
- Analyse architectural requirements and assess potential implementation approaches.
- Collaborate with geographically distributed engineering teams across architecture and development functions.
- Support the development and evaluation of modern CPU core architectures.
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Key Requirements
- 4+ years of relevant experience in CPU architecture, processor architecture, or CPU microarchitecture.
- Strong understanding of Instruction Set Architecture (ISA) and assembly language.
- Knowledge of one or more modern processor architectures, such as Arm, RISC-V, and/or MIPS.
- Strong understanding of modern CPU core microarchitecture.
- Software development experience using C, C++, assembly, and/or Python.
- Experience modelling microprocessors using high-level languages such as C or C++.
- Experience with Advanced Vector Extensions (AVX).
- Knowledge of Arm Scalable Vector Extension (SVE).
- Knowledge of Arm Scalable Matrix Extension (SME).
- Experience with Confidential Compute Architecture (CCA).
Keywords
CPU Architect / CPU Hardware Architect / CPU Architecture / Hardware Architect / Processor Architect / CPU Microarchitecture / Processor Microarchitecture / CPU Core / Processor Design / Instruction Set Architecture / ISA / Assembly / Arm / Arm Architecture / Armv8 / Armv9 / RISC-V / MIPS / C / C++ / Python / Microprocessor Modelling / CPU Modelling / Architectural Modelling / Hardware/ Firmware / Firmware Interfaces / Operating Systems / Hardware/Software Co-Design / Hardware/Software Co-Optimisation / AVX / Advanced Vector Extensions / SVE / Scalable Vector Extension / SME / Scalable Matrix Extension / CCA / Confidential Compute Architecture / Morello / CHERI / Capability Hardware Enhanced RISC Instructions / Compiler Backend / Code Generation / Compiler Architecture / Performance Analysis / Performance Optimisation
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