IC Resources
Design Verification Engineer

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An opportunity has opened for Design Verification Engineers to join one of the most established and highly regarded semiconductor engineering teams in the UK.
The company develops sophisticated mixed-signal ICs used in some of the world’s best-known consumer technology products, giving you the chance to work on complex silicon that ultimately ships at huge scale.
They are hiring at multiple levels, so I’m keen to speak with experienced Verification Engineers through to Senior and Principal-level candidates.
The opportunity
You’ll work across the full ASIC/SoC verification lifecycle, with real ownership of the verification of complex digital subsystems and mixed-signal ICs.
Your Work Will Include
- Developing SystemVerilog/UVM verification environments
- Verification planning and test development
- Constrained-random and coverage-driven verification
- SVA / assertions
- Functional and code coverage
- RTL and testbench debugging
- Verification methodology and infrastructure improvements
- Working closely with design and architecture teams
- Technical leadership and mentoring opportunities at senior levels
Reasons to use Rodeo
I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?
Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.
Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.
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Graduate Consultant — 2026 Scheme
Why you're a good match
StrongYour economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.
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Why you're a good match
You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.
Experience fit
Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.
Only hits
No noise. No "maybe this fits." Just roles with a clear explanation of why they're right — and where to focus when applying.
What they’re looking for
You’ll ideally have a background in ASIC, SoC or Digital IC Verification, with strong experience in:
- SystemVerilog
- UVM
- SVA
- Constrained Random Verification
- Functional Coverage
- RTL Debug
Experience with mixed-signal verification, formal verification, UPF/low-power verification, gate-level simulation or scripting would be particularly valuable.


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Why consider it?
This is a strong option if you want technically challenging verification work without joining a tiny or highly speculative semiconductor business.
You’ll be joining an established global semiconductor company with complex products, experienced engineering teams, long-term career progression and a strong reputation for engineering culture.
📍 Edinburgh or Newbury, UK
🏠 Hybrid – typically 2+ days onsite
📈 Multiple levels available
If you’re a Design Verification Engineer, ASIC Verification Engineer or SoC Verification Engineer interested in hearing more, apply or get in touch with Steph Hutchinson for a confidential conversation.
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