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SoCode Recruitment

Digital Design Engineer

Cambridge
Posted 1 day ago
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Digital Design Engineer (FPGA)

Cambridge | On-site (5 days)

Are you looking to take the next step in your career, continuing an emphasis on Digital Design? Do you want to join a close knit team where you'll receive L&D, support from your colleagues, career growth, and have the ability to work on personal projects in a well-equipped lab?

This is a brand new role in an established digital design team, working in the communications space.

This role puts you at the heart of physical layer design. You'll take ownership of significant blocks of RTL from specification through implementation, verification and into working hardware. You'll work alongside senior and principal engineers who'll support you as you broaden your experience across digital RF, signal processing and the wider product lifecycle, with genuine hands-on lab time and access to serious equipment.

Reasons to use Rodeo

I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?

Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.

Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.

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Grad scheme, placement, apprenticeship? Not sure what you want yet — that's fine. Your agent talks it through with you and turns "I have no idea" into a shortlist.

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Graduate Consultant — 2026 Scheme

PwC·London, UK
£35,000/yr

Why you're a good match

Strong

Your economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.

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It searches the market for you

Every day your agent scans the market matching roles against what actually matters to you, not just keywords on a CV.

Why you're a good match

You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.

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Strong

Experience fit

Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.

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Strong

Only hits

No noise. No "maybe this fits." Just roles with a clear explanation of why they're right — and where to focus when applying.

What You'll Bring:

  • 2+ years' hands-on RTL development for FPGA platforms (Verilog or VHDL)
  • Strong grasp of fixed-point DSP techniques - think filters, FFT implementations, correlators
  • Hands-on experience with AMD/Xilinx FPGA devices and their design toolchain
  • A track record of carrying a design the full distance (from spec, through implementation and test, to hardware that actually works)
  • Comfortable picking up and extending an established codebase, not just starting from a blank sheet
  • A natural communicator who's happy asking questions and working closely within a small, collaborative team
  • Driven to keep learning and sharpening your skills over time

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Also Valued:

  • Exposure to physical-layer RTL for wireless comms - cellular, WiFi, Bluetooth, satellite... any of these are relevant
  • Comfortable using MATLAB for DSP or comms-related work
  • Working knowledge of C or C++ in an embedded context
  • Experience debugging live hardware in a lab setting

This is a team that sticks around. Attrition is genuinely low, and most of the earliest hires are still there. Expect a strong social side outside of work too.

For this role you must be based in the UK and have full right to work. Sponsorship is not provided.

Keen to express your interest, or find out more?

Option 1: Click the apply button (don't worry, we'll discuss your CV before submitting)

Option 2: Drop me a message on LinkedIn

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Skills

RTL Development
FPGA
Verilog
VHDL
Fixed-point DSP
AMD/Xilinx Toolchain
MATLAB
C
C++
Hardware Debugging
Physical Layer Design
Signal Processing

Location

Cambridge, England, United Kingdom

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