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Digital Design Engineer

London
£60k – £70k/yr
Posted about 15 hours ago
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Senior Digital IC Design Engineer

UK | Hybrid | Competitive Salary

An innovative deep-tech start-up developing next-generation computing hardware for autonomous and edge systems is seeking a Senior Digital IC Design Engineer. You’ll play a key role in shaping architecture, driving digital design from concept to tape-out, and collaborating across multidisciplinary teams.

Reasons to use Rodeo

I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?

Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.

Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.

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Graduate Consultant — 2026 Scheme

PwC·London, UK
£35,000/yr

Why you're a good match

Strong

Your economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.

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Why you're a good match

You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.

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Strong

Experience fit

Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.

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Strong

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Key Responsibilities

  • Design and develop digital components
  • Take designs from architecture through RTL coding to the final layout
  • Work closely with other hardware teams to define chip interfaces
  • Create and run simulation and verification plans to ensure the design works correctly

Essential Skills & Experience

  • Strong experience in digital IC design with a focus on computer architecture
  • Proven RTL design experience in Verilog/SystemVerilog
  • Deep understanding of cache hierarchies, bus protocols, memory management units, and task scheduling
  • EDA skills are a bonus

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Apply now to join a pioneering hardware team building the next generation of intelligent computing systems.

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Skills

Digital IC Design
Computer Architecture
RTL Design
Verilog
SystemVerilog
Cache Hierarchies
Bus Protocols
Memory Management Units
Task Scheduling
EDA Tools
Simulation
Verification

Location

London, England, United Kingdom

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