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EVONA

Field-Programmable Gate Arrays Engineer

London
Posted about 22 hours ago
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I’m working with a fast-growing space technology company looking for an Avionics FPGA Engineer to help develop next-generation autonomous space systems.

This is a hands-on role covering the full development lifecycle, from RTL design and simulation through to hardware testing and flight readiness.

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I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?

Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.

Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.

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Graduate Consultant — 2026 Scheme

PwC·London, UK
£35,000/yr

Why you're a good match

Strong

Your economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.

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Why you're a good match

You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.

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Strong

Experience fit

Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.

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They’re looking for experience with:

  • SystemVerilog and/or Verilog
  • FPGA/SoC development
  • RTL design and verification
  • Clock domain crossings, static timing analysis and timing closure
  • SerDes and memory interfaces
  • Hardware debugging using oscilloscopes and logic analysers
  • Python and/or TCL scripting

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Experience with high-speed interfaces, DDR memory, Microchip FPGAs, SoC design or space-rated electronics would be a big plus.

Please note, this position involves access to ITAR-regulated equipment and data, so relevant eligibility requirements apply.

Please apply to find out more!

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Skills

SystemVerilog
Verilog
FPGA/SoC Development
RTL Design
RTL Verification
Clock Domain Crossings
Static Timing Analysis
Timing Closure
SerDes
Memory Interfaces
Hardware Debugging
Oscilloscopes
Logic Analysers
Python
TCL Scripting

Location

London, England, United Kingdom

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