Haley Bridge
Field-Programmable Gate Arrays Engineer

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FPGA Design Engineer, Cambridge (Hybrid)
First few weeks: 3 to 4 days in the office – after these, 1 to 2 days in the office
Salary: This role is open to recent graduates or senior FPGA Engineers – as such, salary is up to £90,000 Base + Benefits depending on experience
About the Role
Our client is an established, award-winning Cambridge-based technology company, focused on the Defence industry. They design and manufacture advanced imaging systems for demanding applications, with in-house R&D and a global reputation for quality. They are now looking for an FPGA Design Engineer to join their FPGA Design Team.
Reasons to use Rodeo
I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?
Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.
Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.
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Graduate Consultant — 2026 Scheme
Why you're a good match
StrongYour economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.
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Why you're a good match
You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.
Experience fit
Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.
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What You'll Be Doing
- Building modules for a shared FPGA library used across the entire product range
- Writing timing constraints, digging into timing reports, and reworking designs to close timing
- Designing for low power, because the kit has to run in the field
- Verifying RTL, ideally with cocotb
- Writing module specs, and reviewing code and documentation with the team
- Working alongside hardware, software, and mechanical engineers to bring new products to market
What You'll Bring


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- SystemVerilog
- Python
- RTL verification experience
- Timing constraints and timing closure
- Low-power design
- Writing clean library code to a coding standard
- Comfort with the Linux command line, Git or SVN, and Markdown
- Teams player with excellent communication skills
- Bonus: experience with cocotb
Why Join?
- Hybrid working, with up to 3 days a week from home after your first few weeks
- Work on cutting-edge imaging technology
- A collaborative team with deep technical expertise
- Training and real career development
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