Chapman Tate Associates
Field-Programmable Gate Arrays Engineer

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Senior to Principal FPGA Engineer
Location
Southampton, Hampshire (Hybrid Working)
Security Clearance
SC Clearance Required or Eligibility to Obtain SC Clearance
We're recruiting for Senior to Principal FPGA Engineers to join a highly capable engineering team working on advanced FPGA, embedded and real-time technology programmes within a secure and technically challenging environment.
This is an opportunity to work on cutting-edge projects involving FPGA design, high-speed digital systems, signal processing and hardware/software integration, contributing throughout the full development lifecycle.
As a Senior or Principal FPGA Engineer, you'll be responsible for the architecture, design, implementation and verification of FPGA-based solutions.
You'll work closely with software, embedded, electronics, systems and verification teams whilst helping shape future technical direction and mentoring junior engineers where appropriate.
Reasons to use Rodeo
I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?
Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.
Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.
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Grad scheme, placement, apprenticeship? Not sure what you want yet — that's fine. Your agent talks it through with you and turns "I have no idea" into a shortlist.
Graduate Consultant — 2026 Scheme
Why you're a good match
StrongYour economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.
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Every day your agent scans the market matching roles against what actually matters to you, not just keywords on a CV.
Why you're a good match
You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.
Experience fit
Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.
Only hits
No noise. No "maybe this fits." Just roles with a clear explanation of why they're right — and where to focus when applying.
Key Responsibilities
- FPGA design and development using VHDL, Verilog or SystemVerilog
- FPGA architecture and implementation
- FPGA verification and validation
- Hardware bring-up and integration
- High-speed digital design
- Hardware/software co-design activities
- Debugging and troubleshooting complex systems
- Working closely with multidisciplinary engineering teams
- Contributing to technical reviews and design decisions
- Supporting projects throughout the full development lifecycle
Experience Required
- FPGA Design & Development
- VHDL, Verilog or SystemVerilog
- FPGA Verification
- Hardware Integration
- High-Speed Digital Design
- FPGA Toolchains (Vivado, Quartus or similar)
- Hardware Debugging & Troubleshooting
- Full Product Development Lifecycle Experience
- Understanding of Embedded Systems


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Desirable Experience
- Xilinx, AMD, Intel (Altera) or SoC FPGA platforms
- Embedded Linux
- C/C++
- Signal Processing / DSP
- High-Speed Interfaces (PCIe, Ethernet, JESD, Aurora, etc.)
- Video Processing Systems
- Communication Systems
- Defence, Aerospace, Telecommunications or Broadcast industries
- Modelsim / QuestaSim
- FPGA-based real-time systems
If you're a Senior, Lead or Principal FPGA Engineer looking for your next challenge, I'd be pleased to arrange a confidential discussion.
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