SwapeTech
Founding Chief Architect (High-Speed SerDes)

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About the Role
We are establishing Swapetech’s UK IC design centre and are looking for a Founding Chief SerDes Architect to lead our in-house SerDes R&D capability. This is a senior technical leadership role for someone who wants to define architecture, build a high-calibre design team, and take ownership of next-generation high-speed interface technology from concept to silicon.
Responsibilities
- Define the long-term architecture and technology roadmap for next-generation high-speed SerDes and PHY solutions.
- Lead the architecture, design direction and technical strategy for advanced mixed-signal interface technologies.
- Drive architectural trade-offs across bandwidth, power, latency, signal integrity, jitter, area, reliability and manufacturability.
- Provide technical leadership throughout the complete silicon development lifecycle, from architectural definition through tape-out, silicon bring-up and production validation.
- Collaborate closely with digital design, verification, physical design, packaging, system architecture and product engineering teams.
- Evaluate emerging technologies and define future product directions aligned with market requirements.
- Represent SwapeTech in technical engagements with customers, industry partners and academic institutions where appropriate.
- Foster a culture of engineering excellence, innovation and technical leadership.
Reasons to use Rodeo
I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?
Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.
Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.
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Graduate Consultant — 2026 Scheme
Why you're a good match
StrongYour economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.
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Why you're a good match
You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.
Experience fit
Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.
Only hits
No noise. No "maybe this fits." Just roles with a clear explanation of why they're right — and where to focus when applying.
Qualifications
- Extensive experience in high-speed SerDes or PHY architecture for advanced semiconductor products.
- Strong expertise in mixed-signal and analog IC design.
- Deep understanding of CDR, PLL, equalisation, clocking architecture, jitter analysis and signal integrity.
- Experience with NRZ and PAM4 signalling.
- Experience with advanced CMOS process technologies.
- Demonstrated experience delivering multiple generations of silicon from architectural definition through tape-out and production validation.
- Proven technical leadership within multidisciplinary semiconductor engineering organisations.
- Excellent communication and stakeholder management skills.


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