Qualified Recruiter, LLC
FPGA design Engineer

How your CV stacks up
Upload your CV to see how well it fits this job role
?%
Job Description – Principal FPGA Design Engineer
Location
Wotton-under-Edge, UK
Working Arrangement
Hybrid – 3 days per week in the office
Key Responsibilities
- Lead FPGA architecture, design, and development from prototype through production.
- Develop and maintain VHDL/Verilog RTL, focusing on performance, reliability, resource optimization, and portability.
- Develop FPGA verification and testbenches using tools such as OSVVM/VUnit.
- Implement, debug, and verify FPGA designs on real hardware.
- Work with embedded algorithms, focusing on performance, accuracy, determinism, and numerical robustness.
- Manage requirements, traceability, design reviews, and code reviews.
- Support functional safety activities and certification where required.
- Produce technical documentation covering architecture, interfaces, timing, verification, and design decisions.
- Mentor and support graduates and apprentices.
- Collaborate across electronics, software, mechanical, and systems engineering teams.
Reasons to use Rodeo
I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?
Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.
Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.
Start with a chat, not a search bar
Grad scheme, placement, apprenticeship? Not sure what you want yet — that's fine. Your agent talks it through with you and turns "I have no idea" into a shortlist.
Graduate Consultant — 2026 Scheme
Why you're a good match
StrongYour economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.
See breakdownIt searches the market for you
Every day your agent scans the market matching roles against what actually matters to you, not just keywords on a CV.
Why you're a good match
You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.
Experience fit
Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.
Only hits
No noise. No "maybe this fits." Just roles with a clear explanation of why they're right — and where to focus when applying.
Key Requirements
- Degree in Electronic Engineering, Physics, or a related discipline.
- Strong experience across the FPGA design lifecycle.
- Excellent VHDL or Verilog RTL development experience.
- Experience with Intel/Altera, AMD/Xilinx, or Lattice FPGAs.
- Strong FPGA verification and testbench experience, ideally with OSVVM.
- Experience implementing and debugging FPGA designs on hardware.
- Strong understanding of:
- FPGA architecture and resource optimization
- Timing constraints and timing closure
- Digital logic and clock-domain crossings (CDC)
- Pipelining
- Embedded systems and microcontrollers
- Signal processing


Get help with your application
Your very own career expert that helps elevate your application to the next level.
Desirable Skills
- C/C++, Assembly, or other embedded programming languages.
- OSVVM, VUnit, MATLAB, Python.
- Git and Azure DevOps.
- High-speed and low-power electronics, including analogue and digital design.
- Experience with IEC 61508 / ISO 13849 or other functional safety standards.
- Experience with continuous integration for FPGA verification.
“It took my CV and asked me questions relevant to understanding what kind of jobs to suggest for me. Suggestions were almost perfect. Jobs were exactly what I’ve been looking for.”
Jessica, London
Skills