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FPGA Engineer - London / Amsterdam
Our client is a highly sophisticated, technology-driven quantitative trading firm operating at the forefront of global markets, where ultra-low latency systems define competitive edge. They are looking to hire a talented FPGA Engineer to design and optimise next-generation trading infrastructure, working across complex FPGA architectures that power real-time decision making. This is a rare opportunity for an FPGA Engineer to build high-performance FPGA solutions from the ground up, directly impacting live trading systems in a fast-paced, globally distributed environment.
They are seeking an experienced FPGA Engineer who thrives in a performance-critical environment and is excited by solving deeply technical challenges at scale. You will work alongside elite engineers and researchers, developing cutting-edge FPGA designs and reusable IP that can be deployed globally. The role offers exceptional exposure to high-speed systems, collaboration across hardware and software teams, and the chance to push the limits of what's possible with modern FPGA technology.
Reasons to use Rodeo
I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?
Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.
Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.
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Graduate Consultant — 2026 Scheme
Why you're a good match
StrongYour economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.
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Every day your agent scans the market matching roles against what actually matters to you, not just keywords on a CV.
Why you're a good match
You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.
Experience fit
Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.
Only hits
No noise. No "maybe this fits." Just roles with a clear explanation of why they're right — and where to focus when applying.
Key Responsibilities
- Design and verify RTL implementations for latency-critical trading systems
- Develop reusable FPGA IP blocks deployable across multiple hardware platforms
- Integrate FPGA designs within a broader low-latency trading stack
- Build automation scripts to optimise workflows and development cycles
- Collaborate closely with software engineers, researchers, and systems teams


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Key Skills
- Strong experience in FPGA/ASIC design and verification
- Proficiency in SystemVerilog, Verilog, or VHDL
- Solid understanding of digital design and hardware architecture
- Experience developing scalable, reusable IP components
- Hands-on knowledge of EDA toolchains
- Strong C++ skills
- Familiarity with scripting (Python, TCL, Bash)
- Degree in Electrical Engineering, Computer Science, or related field
- Exposure to high-speed networking, transceivers, or packet processing (preferred)
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