SoCode Recruitment
FPGA Engineer

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FPGA Engineer
Up to £90k DOE + bonus, healthcare, enhanced pension, etc.
Cambridge (Hybrid) | 3-4 days on site
Our client is looking for an FPGA Engineer to strengthen their permanent team based out of Cambridge.
You'll take ownership of FPGA logic for the controller boards that sit at the heart of the company's hardware, from design through to verification and ongoing maintenance. The work is VHDL-based, targeting Xilinx Artix-7 parts in Vivado, and spans state machine design, low-level driver work (I²C, SPI), test bench development and hands-on hardware testing.
Note that this sits at the discrete-logic and embedded-interfaces level rather than SoC development.
What you'll be doing:
- Writing and implementing VHDL for Xilinx Artix-7 FPGAs in Vivado, following coding standards and taking part in design reviews.
- Designing clean, deterministic state machines to sequence and control hardware interfaces.
- Building driver logic for serial interfaces such as I²C and SPI (UART a plus) - handling initialisation, transactions and error/edge cases.
- Developing self-checking test benches, running simulations, and documenting the verification process.
- Bringing boards up in the lab and validating them with logic analysers and oscilloscopes, debugging as issues arise.
- Handling timing constraints (XDC), clocking, resets and CDC analysis through to timing closure and bitstream generation.
- Feeding into requirements gathering, module-level specs and design reviews, and supporting integration with the wider system.
- Keeping configuration under version control (SVN) and writing up documentation - specs, interface descriptions, test plans, release notes.
Reasons to use Rodeo
I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?
Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.
Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.
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Graduate Consultant — 2026 Scheme
Why you're a good match
StrongYour economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.
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Every day your agent scans the market matching roles against what actually matters to you, not just keywords on a CV.
Why you're a good match
You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.
Experience fit
Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.
Only hits
No noise. No "maybe this fits." Just roles with a clear explanation of why they're right — and where to focus when applying.
What we're looking for:
- Solid, proven VHDL experience on Xilinx devices, and comfortable across the full Vivado flow - constraints, synthesis, place & route, timing closure, bitstream generation.
- Hands-on experience with serial protocols (I²C, SPI, ideally UART too), including the trickier bus arbitration, timing and edge-case scenarios.
- Ability to write self-checking test benches and run simulations (Vivado simulator or similar).
- Comfortable in the lab - bringing up boards, using scopes/logic analysers, and chasing down timing or constraint issues.
- Good grasp of CDC, metastability, reset strategy and synchronous design principles more broadly.
- A strong documenter and communicator who's equally happy working solo or as part of a cross-functional team


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Unfortunately sponsorship is not available for this role.
Keen to express your interest, or find out more?
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Option 2: Drop me a message on LinkedIn (Rachel Bush – SoCode Recruitment)
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