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IC Resources

Hardware Verification Engineer

Cambridge
Posted about 7 hours ago
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Senior Verification Engineer

I am seeking a Senior Verification Engineer to join a rapidly growing HW Team in Cambridge. You will get the opportunity to work on cutting edge technology and in the area of quantum computing. No prior experience in quantum computing? No problem. You’ll learn as you go while working alongside world-class engineers in a truly cross-disciplinary environment.

As a Senior Verification Engineer, you will take ownership of verification across block, subsystem, and multi-FPGA system-level designs.

With visibility across the entire stack, you will partner closely with the Lead Verification Engineer to define and deliver the verification strategy.

Reasons to use Rodeo

I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?

Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.

Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.

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Grad scheme, placement, apprenticeship? Not sure what you want yet — that's fine. Your agent talks it through with you and turns "I have no idea" into a shortlist.

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Graduate Consultant — 2026 Scheme

PwC·London, UK
£35,000/yr

Why you're a good match

Strong

Your economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.

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Why you're a good match

You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.

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Strong

Experience fit

Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.

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Strong

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As a key member of the verification team, you will:

  • Own the strategy and execution for block-level, subsystem, and multi-FPGA system designs
  • Develop scalable UVM-based testbenches that push boundaries
  • Drive verification efforts with a sharp focus on risk, coverage, and system-level behaviour

Key skills

  • Strong hands-on expertise in SystemVerilog and UVM
  • Proven ability to debug across RTL, simulation, and hardware
  • Ability to work effectively with ambiguity and changing requirements
  • Demonstrable commercial experience in functional verification, including ownership of verification planning and strategy
  • Exposure to different programming languages, such as C, C++ and Python
  • Formal verification experience (plus)
  • Experience mentoring junior verification engineers

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The salary range for this role is broad, as they are able to consider varying levels of experience.

For more information contact Rachel Mason at IC Resources.

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Location

Cambridge, England, United Kingdom

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