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IC Resources

IC Layout Engineer

Hampshire
Posted 8 days ago
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New Opportunity for an IC Layout Engineer

This is a new opportunity for an IC Layout Engineer with an expanding Semiconductor company set to revolutionize AI hardware infrastructure. With an office in Southampton, they offer very flexible working arrangements with just a day or so in the office every fortnight.

Working as a member of an experienced team of Analog IC Design and Layout experts, the IC Layout Engineer will support the physical layout of analog and mixed-signal high-speed integrated circuits; converting schematics into high-quality layouts that meet electrical, matching, parasitic, reliability, and manufacturability requirements. You’ll thrive in this small, high-performing team and really make a tangible impact. You’ll play a visible role in shaping products, influencing technical direction, and contributing to the growth of an exciting semiconductor business.

Reasons to use Rodeo

I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?

Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.

Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.

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Graduate Consultant — 2026 Scheme

PwC·London, UK
£35,000/yr

Why you're a good match

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Your economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.

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Why you're a good match

You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.

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Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.

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The Successful IC Layout Engineer Will Have

  • Strong knowledge of analog and mixed-signal CMOS layout techniques, device matching, floorplanning, routing, DRC/LVS/debug, parasitic extraction
  • A good understanding of the best layout practices for advanced semiconductor processes
  • Experience with IC layout tools such as Cadence Virtuoso
  • Experience running and debugging DRC/LVS using tools such as Calibre, Assura, Pegasus, or similar
  • Desirable would be experience with blocks such as PLLs, ADCs, DACs, SerDes, bandgaps, regulators, amplifiers, oscillators, filters, or high-speed I/O

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You can expect a competitive market salary, great colleagues, and the convenience of being able to do a lot of work from home.

For more information or to apply

Contact Caroline Pye @ IC Resources

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Skills

Analog IC Layout
Mixed-Signal Layout
CMOS Layout
Floorplanning
Routing
DRC/LVS
Parasitic Extraction
Cadence Virtuoso
Calibre
Assura
Pegasus
PLLs
ADCs
DACs
SerDes
High-Speed I/O

Location

Hampshire, England, United Kingdom

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