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Qualcomm

IC Package Design Engineer

Cambridge
Posted about 2 months ago
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Company

Qualcomm Technologies International Ltd

Job Area

Engineering Group, Engineering Group > ASICS Engineering


General Summary

About Us

Cambridge is Qualcomm's largest office in the UK, with about 400 team members including engineers, business strategists and support staff. From an engineering perspective, we have teams focusing on:

  • RF and PMU analogue design
  • Digital design & verification
  • Digital physical design
  • Embedded software
  • Packaging and post-silicon validation

Target products include:

  • High performance MODEMs
  • Application Processors
  • Ultra-low power IoT devices
  • Wearables such as smart glasses, smart watches and earbuds

Where you will be working

Cambridge, located in the East of England, 50 miles north of London, is a unique and beautiful city, renowned for its world-class university and the thriving cluster of high technology businesses that have grown up around it. Cambridge is well served by road and rail links, and is within easy distance of the major London airports

About the Role

The Central Hardware Systems Team at Qualcomm has an opening for IC Package Design Engineer. This team is responsible for road mapping, architecting, design methodology, design implementation and verification for all Qualcomm package products.

Principal Duties and Responsibilities

  • Responsible for Package/SIP physical design and layout, optimization, DV, and tape out.
  • Work with multi-functional teams to achieve optimized mechanical, electrical RF & SI/PI, and thermal performance for various types of chips.
  • Work with IC Physical Design team on top level floor planning including hard macro block placement, Redistribution Layer, and bump/ball pattern/assignment.
  • Drive methodology, innovations, and efficiency improvements in package design together with vendors and developers on feature development and bug resolution.
  • Explore, evaluate, and develop new CAD tools, design, and verification flow.
  • Working with marketing/IC/product teams on competitive analysis and road mapping package technology for future products.

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Minimum Qualifications

  • Bachelor's degree in Science, Engineering, or related field.

Preferred Qualifications

  • Master's degree or PhD in Electronic Engineering, Material Science, or related field.
  • Basic knowledge in high-speed IO interfaces and electromagnetic field.
  • Knowledge of IC packaging structures and package-board interaction.
  • Basic knowledge of electronic packaging process and typical failure modes preferred.
  • Proven fundamentals in electrical, material, thermal, or mechanical engineering fields.
  • Familiarity with various sophisticated package configurations and assembly/substrate technology (Flip chip BGA, 2.5D/3D Interposer, etc.).
  • Experience in package design and proficiency in Cadence Allegro platform tools (PCB Editor, Advanced Package Designer, APD/SiP).
  • Basic understanding of some SI/PI tools (XtractIM, PowerSI, HFSS, Q3D, etc.), package model extraction, S-parameters, and RLGC model.
  • Basic knowledge of substrate manufacturing process, structure, design rules, and material properties.
  • Proven understanding of RF and high-speed interfaces, including DDR, PCIe, UCIE, etc.
  • Experience with Calibre tool and package design reviews.
  • Knowledge of high-speed layout constraints (crosstalk mitigation, differential pairs).
  • Solid understanding of Design Rules Check and Design for Manufacturing.
  • Experience with 2.5D Si-Bridge design in Virtuoso or similar CAD tools is a plus.

What's on Offer

  • Salary, stock and performance related bonus
  • Maternity/Paternity Leave
  • Employee stock purchase scheme
  • Matching pension scheme
  • Education Assistance
  • Relocation and immigration support
  • Life, Medical, Income and Travel Insurance
  • Subsidised gym membership
  • Bicycle purchase scheme

References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

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Qualcomm Commitment

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.


Agency Notice

To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.


If you would like more information about this role, please contact Qualcomm Careers.

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Skills

IC Package Design
Physical Design
Layout Optimization
Cadence Allegro
SI/PI Analysis
RF Performance
Thermal Performance
Flip Chip BGA
2.5D/3D Interposer
Calibre
Design For Manufacturing
High-Speed IO Interfaces

Location

Cambridge, England, United Kingdom

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