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Lead FPGA Engineer

Slough
Posted about 16 hours ago
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Lead FPGA Engineer

Location: Berkshire, Onsite
Job Type: Permanent, Full time
Clearance: Eligibility for DV
Salary: Competitive + Bonus + DV allowance

We are working with a leading organisation in the defence and secure communications sector, and we’re looking for an experienced Principal FPGA Engineer to join their team.

This is a senior technical role where you’ll take ownership of FPGA/firmware development from requirements and architecture through to implementation, integration and verification, while providing technical leadership and mentoring to other engineers.

  • Lead FPGA/firmware architecture, design, development and verification.
  • Develop and review firmware requirements, designs and technical documentation.
  • Provide technical leadership across complex engineering projects.
  • Support design reviews and project planning.
  • Mentor and develop less experienced engineers.
  • Drive improvements to firmware development processes and best practice.

Reasons to use Rodeo

I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?

Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.

Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.

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Grad scheme, placement, apprenticeship? Not sure what you want yet — that's fine. Your agent talks it through with you and turns "I have no idea" into a shortlist.

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Graduate Consultant — 2026 Scheme

PwC·London, UK
£35,000/yr

Why you're a good match

Strong

Your economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.

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Why you're a good match

You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.

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Strong

Experience fit

Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.

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Strong

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What We’re Looking For

  • Strong experience across the full FPGA/Firmware development lifecycle.
  • Extensive VHDL experience.
  • Experience with FPGA platforms such as Xilinx, Lattice, Altera/Intel or Microsemi.
  • Strong knowledge of FPGA verification and EDA tools.
  • Experience with digital hardware design and reading schematics.
  • Knowledge of communications protocols such as UART, SPI, I2C, TCP/IP and UDP.
  • Experience working with structured engineering methodologies such as the V-Model.
  • Strong technical leadership, problem-solving and communication skills.

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Benefits

  • Annual bonus
  • Private medical cover
  • 25 days’ holiday + Bank Holidays
  • Pension contribution
  • 4x life assurance
  • Flexible working
  • Early Friday finish
  • Flexible benefits package
  • Security clearance allowance, where applicable
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Location

Slough, England, United Kingdom

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