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Baya Systems

Microarchitect & RTL Designer

Cambridge
Posted about 1 month ago
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Job Title: Microarchitect & RTL Design Engineer

Location: Cambridge, England, United Kingdom

About the Role:

We are seeking a seasoned Microarchitect and RTL Design Engineer with a strong background in microarchitecture and RTL coding. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions.

Key Responsibilities:

  • Design and develop microarchitectures for a set of highly configurable IPs
  • Microarchitecture and RTL coding ensuring optimal performance, power, area
  • Collaborate with software teams to define configuration requirements, verification collaterals, etc.
  • Work with verification teams on assertions, test plans, debug, coverage, etc.

Reasons to use Rodeo

I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?

Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.

Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.

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Graduate Consultant — 2026 Scheme

PwC·London, UK
£35,000/yr

Why you're a good match

Strong

Your economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.

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Why you're a good match

You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.

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Strong

Experience fit

Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.

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Strong

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Qualifications:

  • BS, MS in Electrical Engineering, Computer Engineering, or Computer Science
  • 8+ years and current hands-on experience in microarchitecture and RTL development
  • Proficiency in Verilog, System Verilog
  • Familiarity with industry-standard EDA tools and methodologies
  • Experience with large high-speed, pipelined, stateful designs, and low power designs
  • In-depth understanding of on-chip interconnects and NoCs
  • Experience within ARM ACE/CHI or similar coherency protocols
  • Experience designing IP blocks for caches, cache coherency, memory subsystems, interconnects, and NOCs
  • Familiarity with RAS designs, QoS in fabrics, PCIe/IO is a plus
  • Experience with modern programming languages like Python is a plus
  • Excellent problem-solving skills and attention to detail
  • Strong communication and collaboration skills

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Contact: rich.goldstein@bayasystems.com

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Location

Cambridge, England, United Kingdom

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