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weeteq

Principal Software Engineer

Glasgow
Posted about 20 hours ago
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Principal Software Engineer

weeteq — Glasgow, UK · Full-time · Ultra Edge® platform

weeteq builds real-time power and control intelligence. We're hiring a Principal Software Engineer to architect the firmware and SDK for weeteq and third-party MCUs — the timing and telemetry pipelines that manage hardware-level state transitions and system-level optimisation under dynamic AI workloads.

This is a senior, hands-on leadership role. You set the technical direction for our software, lead the engineers who build it, and own the development process end to end: architecture through delivery on silicon-close, real-time systems. You'll lead development of highly optimised RTOS environments, design the APIs for system-level integration, and drive pre-silicon validation on FPGA.

The mandate: lead the software development, own the process. You are the expert accountable for how we design, build and validate the code that runs inside the control loop.

Leading the software

  • Set technical direction — own the architecture and engineering standards across embedded, real-time and ML-on-device workstreams, and make the hard build-versus-buy calls.
  • Lead the engineers — mentor and technically line-manage a growing team (today 8 technical staff plus contractors), set the quality bar, review critical code, grow people into their next level.
  • Be the senior voice — represent software in leadership decisions, roadmap planning and technical due diligence with customers, partners and investors.
  • Deliver hands-on — stay close to the code, unblock the team, personally own the hardest problems.

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I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?

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Graduate Consultant — 2026 Scheme

PwC·London, UK
£35,000/yr

Why you're a good match

Strong

Your economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.

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Why you're a good match

You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.

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Owning the process

  • Define how we build — the full lifecycle: architecture, coding standards, version control, code review, CI/CD, testing, release management.
  • Engineer for real-time — the verification, validation and traceability practices demanded by safety- and timing-critical embedded systems.
  • Drive quality and cadence — delivery predictability, technical debt, tooling and documentation as the team scales.
  • Bridge hardware and software — partner with silicon and systems engineering from concept to chip.

What you'll build

  • Ultra-lightweight microkernel RTOS environments (Zephyr / FreeRTOS) tuned for sub-millisecond loops, with hard real-time, zero-jitter scheduling across high-frequency I3C timing transitions.
  • Developer-facing HALs and secure APIs exposing I3C hardware blocks to the BMC.
  • Low-latency telemetry pipelines capturing voltage, current and temperature at microsecond intervals, and interrupt-driven firmware that parses events such as sudden dI/dt spikes from AI training and inference state shifts.
  • Predictive power management via I3C In-Band Interrupts, preventing server throttling.
  • Hardware-in-the-loop firmware on FPGA emulation platforms (Xilinx UltraScale+, Intel Stratix / Agilex), RTL co-verification with digital design, and timing validation using Vivado ILA / SignalTap.

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What you bring

  • Expert-level C / C++ for resource-constrained, real-time targets, with a strong grasp of DSP, control systems or on-device ML.
  • RTOS mastery — custom drivers, memory management and thread schedulers in Zephyr, FreeRTOS or proprietary real-time microkernels.
  • Systems thinking: comfortable silicon-close, across the hardware/software boundary, from concept to chip.
  • Familiarity with the power profiles, sideband management needs and OCP standards governing AI accelerator clusters and GPUs.
  • Hands-on FPGA toolchains — flashing, debugging and running embedded software on bare-metal prototypes.
  • Technical leadership — you set direction, lead the engineers, and own the development process end to end.

Why weeteq

Own the software function of a fabless semiconductor company at the moment it scales — genuine principal-level scope. Work on a real industry problem: the AI power crisis, the 800V transition, and the transients legacy control can't handle. Proven traction — OCP best-paper winner, test chip in hand, cash-flow positive, Silicon Catalyst and Arm partners.

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Skills

C
C++
RTOS
Zephyr
FreeRTOS
FPGA
Embedded Systems
Firmware Architecture
DSP
Control Systems
I3C
CI/CD
Technical Leadership
Hardware-in-the-loop
API Design
Memory Management

Location

Glasgow, Scotland, United Kingdom

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