Areas Of Particular Interest For This Post Include

• Advanced packaging architectures — 2.5D silicon interposer, 3D hybrid bonding, fan-out WLP/PLP, glass interposers — and their physical-design implications.
• Back-end EDA and physical implementation for multi-die stacks — place-and-route, cross-die DRC/LVS, packaging parasitics extraction, packaging-aware timing and signal/power-integrity sign-off.
• Known-good-die test methodology and its relationship to physical implementation; reliability, qualification, and manufacturing yield.
• The UK and global supply chain for HI — OSAT and foundry pathways, compound-semiconductor assembly, and its interface with silicon back-end processes.
• Sustainability, lifecycle assessment, and embodied-carbon modelling applied to packaging and assembly.

All four cross-cutting constraints — design-for-test (DfT), design-for-power-delivery (DfP), design-for-security (DfS), and design-for-thermal-extraction (DfTh) — span the logical-physical boundary, and both post holders are expected to develop working familiarity with them regardless of primary domain.

No candidate need span all areas. Strong credibility in one area of advanced packaging, semiconductor test, back-end physical implementation, or supply-chain analysis is the core requirement; depth in one or more of the complementary areas above is welcomed.

We particularly welcome applicants whose work has bridged from adjacent backgrounds — materials, devices, sensors, photonics, RF, power electronics (GaN/SiC), or board-level integration — into packaging, assembly, test, and integration work. To be clear, the focus is on the systems-and-integration direction; candidates whose current work is still on the device-physics or process side are out of scope for this post, as that capability is well covered elsewhere in the QSS Group, through CHIMES² partners (notably Imec), and through national semiconductor programmes.

Main Duties And Responsibilities

Technology landscape and roadmap

• Lead WP1 Activities: Direct structured landscape analyses mapping integrator needs for maturing-TRL devices, circuits, and interposers across back-end EDA capability, advanced packaging architectures, and manufacturing transitions.
• Maintain CHIMES² Roadmaps: Develop physical implementation and manufacturing roadmaps (EDA gaps, known-good-die test, reliability, yield) benchmarked against IEEE HIR, EU APECS, DARPA NGMM, JEDEC, IPC, SEMI, and EDA vendor roadmaps (Siemens, Synopsys, Cadence).
• Analyze Heterogeneous Integration (HI) Gaps: Evaluate HI EDA gaps (cross-die timing closure, DfT test access, DfP/backside power delivery, DfTh thermal extraction, and tamper-evident physical security).
• Logical-to-Physical Handoff: Perform gap analysis where physical execution fails architectural intent (parasitic extraction, packaging-aware sign-off) to inform Design Commons guidance.

Leadership and ecosystem engagement

• Represent & Network: Act as CHIMES² ambassador at global forums (iMAPS, IEEE ECTC, TechWorks DESN), engaging OSATs, foundries, EDA vendors, standards bodies (UCIe), and UK agencies (CSA Catapult, NEF, NPL).
• Policy & Strategy: Contribute technical intelligence to government consultations, policy briefings, Advisory Boards, and companion RIF initiatives.
• Programme Synthesis: Work across domain-specific CHIMES² leads to aggregate research college inputs into coherent roadmap assets, collaborating with the companion RIF on logical-to-physical handoff methodologies.
• Internal Integration: Partner with the Sheffield engineering team to feed demonstrator programs, support skills-building, and synthesize research into unified roadmap assets.

Knowledge asset creation

• Deliverables & Guidance: Author Design Commons white papers, capability maps, and WP3 demonstrator briefs aligned with international benchmarks (SRC JUMP 2.0, EU Chips JU).
• Independent Research: Establish a high-impact research theme in heterogeneous integration to build toward future fellowship or academic applications.
• Academic Output: Co-author peer-reviewed publications, present at major conferences, and contribute domain intelligence to secure future funding extensions.

Research, authorship, and translation

• Independent Research: Establish a CHIMES²-aligned research theme in heterogeneous integration, endorsed by the Director, to form the basis for future fellowship or first-academic-post applications.
• Publishing & Authorship: Serve as named author on Design Commons assets and policy briefings, developing them into peer-reviewed outputs and conference presentations.
• Academic Translation: Collaborate with Co-Investigators and PDRAs to keep landscape work grounded in research frontiers and contribute intelligence to future funding applications and extensions.
• Carry out other duties, commensurate with the grade and remit of the post.

Person Specification

Our community welcomes diverse backgrounds and experiences. We particularly encourage applications from researchers in their first postdoctoral position, and from researchers in a second postdoctoral role who would prefer a post of this kind to moving directly to a lectureship, and from candidates whose work has bridged from adjacent backgrounds (materials, devices, sensors, photonics, RF, quantum hardware, FPGA, embedded systems, or high-speed PCB / board-level integration) into circuit, system, and integration work. Even if your past experience doesn’t match perfectly with this role’s criteria, your contribution is valuable, and we encourage you to apply. Please ensure that you reference the application criteria in your application statement.

Applicants must provide the following documents when making their application — Please upload a merged PDF document under the Cover Letter section on our application system:

• CV (including a list of publications