Why this role is distinctive

• It is a national-programme intelligence role. You will lead landscape and roadmap work that directly shapes CHIMES² research priorities, demonstrator projects, and the Design Commons — work with reach across the UK ecosystem, not confined to a single lab.
• It is a deliberate platform to launch from. The post is designed to let you build a visible, fundable independent research identity and the track record to launch it — whether toward a research fellowship (RAEng, UKRI FLF, MSCA, ERC Starting), a first permanent academic appointment, or a senior role in the national semiconductor ecosystem. The four-year term gives genuine room to figure out which of those is right for you and to become competitive for it.
• You will be a named representative of CHIMES² externally — at IMAPS, IEEE ECTC, DATE, Hot Chips, TechWorks DESN, and equivalent forums — and a named author on Design Commons white papers, capability maps, and policy briefings produced from your work.

Areas Of Particular Interest For This Post

• System partitioning and chiplet decomposition methodologies; cross-die interface specification frameworks.
• System-technology co-optimisation (STCO/XTCO) and mission-aware partitioning under power, thermal, and security constraints.
• Front-end and system-level EDA for multi-die design — partition-aware synthesis, architectural exploration, system-level floor planning, cross-die timing, die-to-die interface IP.
• Chiplet interconnect standards (UCIe, CXL, die-to-die PHY) and interoperability frameworks (3Dblox, OIF).
• Open Design Commons infrastructure and open-source EDA / RISC-V IP ecosystems.

All four cross-cutting constraints — design-for-test (DfT), design-for-power-delivery (DfP), design-for-security (DfS), and design-for-thermal-extraction (DfTh) — span the logical-physical boundary, and both post holders are expected to develop working familiarity with them regardless of primary domain.

No candidate need span all areas. Strong credibility in logical systems architecture and front-end design is the core requirement; depth in one or more of the complementary areas above is welcomed.

We particularly welcome applicants whose work has bridged from adjacent backgrounds — computer architecture, embedded systems, FPGA-based research, accelerator or hardware-software co-design, low-power or sensor or quantum-hardware systems, or high-speed PCB / board-level integration — into circuit, system, and integration work. To be clear, the focus is on the systems-and-integration direction; candidates whose current work is still on the device-physics or process side are out of scope for this post, as that capability is well covered elsewhere in the QSS Group, through CHIMES² partners (notably Imec), and through national semiconductor programmes.

Main Duties And Responsibilities

Technology landscape and roadmap

• Lead the WP1 logical systems architecture domain landscape activities — structured analysis of the needs of integrators and of those seeking to integrate maturing-TRL device, circuit, or interposer propositions — covering system partitioning, chiplet decomposition, cross-die interface specification, and STCO/XTCO approaches across the UK and international HI community.
• Develop and maintain CHIMES² roadmaps for the logical architecture and front-end design domain, cross-referencing international roadmap assets including IEEE HIR, EU APECS, DARPA CHIPS/NGMM, SRC JUMP 2.0, imec STCO, and interoperability standards (UCIe / 3Dblox / OIF / CXL).
• Analyse front-end EDA tool gaps for heterogeneous integration — partition-aware synthesis, multi-die timing closure, DfT insertion at the chiplet boundary, DfS architectural patterns, power-intent specification across dies (UPF/CPF), and thermal-aware floorplanning.
• Conduct structured gap analysis identifying integration-specific design challenges underserved by current UK and international R&D, particularly in multi-vendor chiplet EDA flows, STCO, and open Design Commons infrastructure.

Leadership and ecosystem engagement

• Represent CHIMES² at national and international events and policy forums (IMAPS, IEEE ECTC, TechWorks DESN, DATE, Hot Chips, and equivalent), and build relationships across the design, EDA, foundry/OSAT, and standards communities (IEEE, JEDEC, IPC, SEMI, UCIe Consortium).
• Contribute technical intelligence to CHIMES² business and policy development — government consultation responses, policy briefings, and the programme’s strategic positioning — and communicate landscape findings to the Advisory and Technical Advisory Boards.
• Work collaboratively with domain-specific PDRAs recruited by CHIMES² Co-Investigators, aggregating contributions across the research college into coherent programme-level roadmap assets, and collaborate with the companion RIF on the logical-to-physical handoff methodology.
• Work closely with the CHIMES² Sheffield engineering team, contributing CTO Office intelligence to Design Commons and demonstrator delivery and to the programme’s skills-building activities.

Knowledge asset creation

• Lead the development of Design Commons white papers, capability maps, and curated landscape reports in your domain, translating complex technical and ecosystem intelligence into outputs accessible to both technical and policy audiences.
• Apply and help shape the CHIMES² roadmapping methodology (technology roadmapping, systems thinking, gap analysis), ensuring outputs align with international benchmarks (IEEE HIR, EU Chips JU, DARPA NGMM, SRC JUMP 2.0).
• Contribute to co-created WP3 demonstrator project briefs and to Annual Reports, milestone deliverables, and Flexible Funding call documentation.

Research, authorship, and translation

• Develop an independent research theme arising from your landscape and roadmap work, with protected time agreed in the workplan at appointment and signed off by the CHIMES² Director. This theme is expected to intersect with CHIMES²’s heterogeneous-integration mission and to form the basis of future fellowship or first-academic-post applications.
• Be a named author on CHIMES² Design Commons white papers, capability maps, and policy briefings, supported to develop these into peer-reviewed outputs and conference presentations.
• Collaborate with Co-Investigators and PDRAs to keep landscape work grounded in current research frontiers, and contribute to future funding applications and programme extensions.
• Carry out other duties, commensurate with the grade and remit of the post.

Person Specification

Our community welcomes diverse