Research Engineer: AI for CPU Architecture (Contractor)

Job Summary

We are seeking an ambitious Research Engineer to work at the intersection of machine learning and CPU microarchitecture on the Kirin CPU Team at Huawei R&D UK (Cambridge). You will use reinforcement learning, LLM agents and learned models to discover and validate improvements for next-generation out-of-order CPU cores, including agentic systems that turn research papers into simulated, measured results. This role suits someone early in their career who is equally comfortable in a cycle-accurate simulator and a training loop, and who has built systems from scratch because they wanted to understand how they work.

Key Responsibilities

• Build RL, Bayesian and LLM-agent-driven design-space exploration over gem5 and cycle-accurate models, using fast simulation for broad search and detailed models to validate the shortlisted candidates.
• Develop agentic pipelines that read architecture papers, implement the proposed mechanisms in simulators, run experiments and verify results, including the reward design, sandboxing and checks that catch invalid or reward-hacked outcomes.
• Train surrogate and ML performance models that predict IPC and PPA impact and reduce simulation cost.
• Characterise emerging workloads on CPUs, such as on-device LLM inference, matrix and vector extensions, and KV-cache memory behaviour, and translate the findings into microarchitecture proposals.
• Attribute performance bottlenecks as hardware-fixable, software-fixable or joint, and work with compiler, runtime and kernel engineers on co-design solutions.
• Turn strong results into patents, internal reports and, where appropriate, publications.

This job description is only an outline of the tasks, responsibilities and outcomes required of the role. The jobholder will carry out any other duties as may be reasonably required by his/her line manager. The job description and personal specification may be reviewed on an ongoing basis in accordance with the changing needs of Huawei Research and Development UK Limited.

Required

• Degree in Computer Science, Computer Engineering, Electrical Engineering or a related field (BSc, MSc or PhD), or equivalent practical experience.
• Solid understanding of out-of-order CPU microarchitecture, including speculation, branch prediction, prefetching, caches and the memory hierarchy.
• Strong C++ and Python.
• Hands-on depth in at least two of the following:
  • Architectural or cycle-accurate simulation (gem5, ChampSim, Scarab or similar)
  • Reinforcement learning or model training and post-training (PPO, GRPO or similar)
  • LLM agent systems and tool-driven automation
  • Compilers or low-level performance kernels (LLVM/MLIR, CUDA/Triton, SIMD)
• Evidence of building a non-trivial system end-to-end, such as an open-source project, a simulator extension, a compiler, a runtime or a tool you designed yourself.
• Rigorous experimental methodology and the ability to read research papers critically.

Desired

• PhD (completed or in progress) in computer architecture or ML systems.
• Publications at ISCA, MICRO, HPCA or ASPLOS, or at MLSys, NeurIPS or ICML.
• Experience with ML-based prefetchers or branch predictors, including CBP or DPC championship entries.
• Familiarity with ARMv9 (SVE2, SME2) or RISC-V.
• Understanding of the hardware cost of microarchitecture features (storage, timing and power), without RTL design responsibility.
• Open-source contributions to gem5, ChampSim, LLVM/MLIR, or your own language, runtime or ML framework.