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SC Cleated FPGA Engineer

London
£650/day
Posted about 10 hours ago
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Job Title: SC Cleared Senior FPGA / Embedded Systems Engineer (Xilinx Zynq UltraScale+ & Yocto)

Location

Hybrid/London/Bristol as and when required

Rate

Up to £650 per day Outside IR35

Duration

6 months with possible extension

Must be willing and eligible to go through the SC Clearance process

About the Role

Our Client is hiring for a reputed client seeking a hands-on FPGA and embedded Linux expert to help design, integrate and verify high-performance hardware and software components. If you enjoy working at the boundary of silicon and systems-optimising throughput, latency and power-this could be a fantastic next step.

What You'll Be Doing

  • Design, implement and verify custom FPGA IP modules, DSP pipelines and high-speed communications interfaces using VHDL or Verilog/SystemVerilog in AMD/Xilinx Vivado
  • Lead SoC hardware/software co-design by configuring and integrating the Processing System (PS) and Programmable Logic (PL) on Zynq UltraScale+ devices, using AXI interfaces
  • Build, maintain and customise embedded Linux components including Linux BSPs, device trees, U-Boot and kernel images using Yocto Project / PetaLinux
  • Develop low-level Linux device drivers, kernel modules, and bare-metal/FreeRTOS drivers to connect application software with custom hardware IP
  • Carry out board bring-up, debugging and system verification using tools such as logic analysers, oscilloscopes and Vivado ILA
  • Contribute to system-level architecture decisions across throughput, latency, power budgets, and hardware-vs-software partitioning

Reasons to use Rodeo

I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?

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Graduate Consultant — 2026 Scheme

PwC·London, UK
£35,000/yr

Why you're a good match

Strong

Your economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.

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Why you're a good match

You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.

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Strong

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Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.

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What You'll Bring

  • Proven commercial experience designing with AMD/Xilinx Zynq UltraScale+ MPSoC architectures
  • Strong proficiency with Vivado Design Suite, IP Integrator and simulation workflows (e.g., ModelSim, Questa or Vivado Simulator)
  • Solid HDL capability across VHDL, Verilog and/or SystemVerilog
  • Demonstrable experience with Yocto (BitBake, recipe creation, layer management) or PetaLinux for building custom Linux distributions
  • Strong C/C++ skills for Linux kernel-space driver work, device tree customisation and hardware abstraction layer (HAL) development
  • A practical, investigative approach to debugging and verification-comfortable working through complex hardware/software issues

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Additional Information

Successful candidates are likely to enjoy collaborating on architectural trade-offs and performance optimisation, with an engineering mindset that balances system requirements with real-world constraints

If you're an FPGA/embedded Linux engineer who thrives on co-design, verification and performance optimisation, we'd love to hear from you. Apply now to be considered.

If you receive suspicious outreach claiming to be from us, please contact us via the ManpowerGroup website.

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Skills

FPGA Design
Embedded Linux
Xilinx Zynq UltraScale+
VHDL
Verilog
SystemVerilog
Yocto Project
PetaLinux
C/C++
Vivado Design Suite
AXI Interfaces
Device Drivers
Board Bring-up
DSP Pipelines
SoC Co-design
SC Clearance

Location

London, England, United Kingdom

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