ABOUT FRACTILE

Fractile was founded in 2022 on the bet that, eventually, the world’s most capable AI systems would be limited in their impact by the time taken to produce useful outputs. We bet everything on the logical conclusion: that the only way to truly unlock this latent value, to make speed viable at scale, was to radically re-invent the hardware that we run our frontier AI models on. Ever since, we have been building chips and systems that tackle this problem: how to efficiently generate output at thousands of tokens per second, while handling the complexity and capacity challenges of operating large models at very long contexts.

The workloads that push to the limits of the current frontier are already transformational; it is the technical and economic limits on inference speed that are constraining progress. The defining work of the 21st century will be marked by the engine of inference delivering immense and diffuse chains of intellectual inquiry, in drug discovery, in software engineering, in materials discovery, in any field where progress is driven by deep reasoning and intelligence to resolve complex problems.

Summary

We are seeking an experienced Semiconductor Test Engineer to lead the development and deployment of manufacturing test solutions for next-generation AI accelerator devices. This role spans the full silicon lifecycle from first silicon bring-up through high-volume production, with responsibility for defining test strategy, developing ATE test content, debugging complex silicon issues, and optimizing yield, coverage, and test cost. The ideal candidate will bring deep expertise in DFT methodologies, high-speed interface testing, and advanced CMOS manufacturing, and will work closely with design, DFT, packaging, and manufacturing partners to ensure robust, scalable production of high-performance compute silicon.

Key Responsibilities

• Develop and maintain ATE test programs for an AI accelerator chip targeting high-volume manufacturing.
• Implement manufacturing test content for advanced CMOS designs including high-speed logic, SRAM, DRAM, and high speed IO blocks.
• Develop and debug structural and functional test content such as scan/ATPG, LBIST, MBIST, JTAG, and HSIO tests.
• Bring up first silicon on ATE, including pattern debug, tester correlation, shmooing, and corner analysis.
• Support testing of high-speed interfaces such as PCIe Gen6 and multi-GHz LPDDR, including at-speed tests and margining features.
• Execute silicon characterization and failure analysis to identify yield limiters and defect mechanisms.
• Optimize test coverage, test time, and cost while maintaining manufacturing robustness.
• Work with DFT and design teams to improve testability and close coverage gaps.
• Collaborate with OSATs and external partners on test program execution and debug.
• Support advanced packaging test flows, including die-to-die interconnect testing and package-level thermal considerations.
• Contribute to documentation of test programs, debug procedures, and manufacturing release materials.
• Support qualification, reliability testing, and high-volume manufacturing ramp.