Fractile
Senior Compute Architect

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Fractile Processor Architect
Fractile is building silicon, systems and software which will redefine the frontier of AI: running the world’s most advanced models at radically higher speed and lower cost. We have an exceptional team across hardware and software capable of bringing about this change, and we are growing fast to meet demand and deliver our product at scale.
As Processor Architect, you'll define and drive the architecture of our core compute engines, ISA definitions and programming models through to memory hierarchies, and on-chip interconnects. This isn't just about hitting PPA targets on a spreadsheet; you'll work closely with logical design, physical design, and verification teams to translate architectural intent into working silicon that performs in the real world. Expect to be hands-on in performance modelling, detailed specification writing, bottleneck analysis, pre and post-silicon validation. You'll be the driving force behind the computational heart of our products ensuring every cycle counts and every watt is well spent.
Key Responsibilities
- Define and own the compute engine architecture specifications, balancing performance, flexibility, power, area, and design complexity.
- Lead architectural exploration from early concept through to specification, coordinating with modelling, implementation, verification, and physical design teams.
- Specify execution units, memory hierarchy, instruction sets and flow — making principled trade-offs at every level.
- Help build and maintain performance models and simulators to guide architectural decisions with data.
- Partner with the system architecture and software/modelling teams to ensure the processor delivers real-world application performance, not just benchmark wins.
- Evaluate emerging techniques — compact number formats, novel compute paradigms, advanced packaging options — to inform the architectural roadmap.
- Act as a technical mentor, raising the bar for rigour in performance analysis and architectural documentation across the team.
- Represent compute engine architecture in technical reviews, partner discussions, and customer engagements.
Reasons to use Rodeo
I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?
Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.
Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.
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Graduate Consultant — 2026 Scheme
Why you're a good match
StrongYour economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.
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Why you're a good match
You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.
Experience fit
Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.
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Skills & Experience
- Proven experience as a Processor Architect, CPU/GPU Architect, or similar role in semiconductor or high-performance computing domains.
- Deep understanding of compute engine and processor architecture and design, including matrix and vector centric floating-point arithmetic and memory hierarchies.
- Strong grasp of RTL design flows and physical design constraints and how they feed back into architectural choices.
- Experience taking processor designs from early exploration through to tapeout and post-silicon performance characterisation.
- Demonstrated ability to define and manage performance and power budgets and navigate complex trade-offs.
- Comfortable working across many disciplines, including architecture, modelling, implementation, verification, and software.
- Excellent communicator who can bridge architectural depth with system-level and product-level context.


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Desirable
- Background in AI acceleration, vector/matrix compute, or domain-specific processor design.
- Experience with architectural performance modelling tools and frameworks (gem5, SystemC, custom cycle-accurate simulators).
- Familiarity with compiler and toolchain interactions, understanding how software maps to hardware.
- Prior start-up or scale-up experience, someone who thrives in ambiguity and fast iteration.
How We Work
- Ownership and execution: you will have full agency to drive your work forward
- Rapid iteration: we all work directly with top leadership to move from idea to hardware on ambitious timelines
- Full-stack engagement: hardware, software, silicon, and modelling teams all work closely together to create a product with generational impact
- Optimistic and pragmatic: we possess the will to win, and to do the hard work to get us there
- Team player mentality: the mission is bigger than any of us, and we have the curiosity and technical focus to see the best idea shipped, no matter whose it is
About Us
- Founded in 2022, a team of 80+, which is expanding rapidly
- Modern, open offices in London and Bristol
- Collaborative, problem-solving culture built on deep curiosity, entrepreneurial initiative and technical fluency
Export control and security clearance
Certain roles may involve working on technologies subject to export restrictions. Applicants may be required to undergo additional eligibility checks to ensure compliance with applicable law.
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