TRIA
Senior Design Engineer
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Senior RTL Design Engineer
📍 Leeds (onsite) | 💰 £70,000 – £90,000 + bonus | Permanent
We're working with a pioneering UK deep-tech company building programmable silicon photonic compute, technology that performs operations directly within the data path instead of constantly moving data back and forth. Their work underpins breakthroughs in AI, cybersecurity and scientific research. They're a small, high-calibre team, so every hire makes a real difference.
They're looking for a Senior RTL Design Engineer to lead RTL architecture and digital top-level integration for the logic surrounding their photonic compute path. In short, you'd be the person making the digital side of a genuinely novel chip work.
What we're after
- ✅ 8+ years of ASIC RTL design and digital top integration
- ✅ Advanced SystemVerilog/Verilog, with a strong grasp of synthesis and timing constraints
- ✅ High-speed serial interfaces (PCIe, CXL, UCIe, AXI/AMBA) and memory interfaces (DDR5, LPDDR, HBM)
- ✅ Solid CDC, reset design, low-power and hardware debug experience
- ✅ A track record of taking designs through tapeout with mixed-signal and physical design teams
- ✅ Bonus points for 7/12nm, Cadence flows, Python/Tcl or any photonics exposure
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What's in it for you?
- 💰 £70k–£90k base plus annual performance bonus
- 🏥 Comprehensive healthcare
- 🏦 Employer-contributed pension
- 🏋️ Gym membership claim-back
- 🚆 Season ticket travel support
- 🏖️ Generous time off
This isn't a "maintain the block someone else built" role. You'll define the digital top architecture from the ground up, including clock and reset strategy, register maps and block-level interfaces. You'll also write synthesizable RTL for control state machines, data paths, side channels and custom PCS/MAC sub-layers.
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You'll work hand in hand with photonics, analogue, verification and layout engineers, including the Director of Photonics. Your work will go right through tapeout and first-silicon bring-up in the lab. Few RTL roles in the UK put you this close to something this new.
If you want a role where your architecture decisions shape what a new class of compute can do, I'd love to hear from you.
Apply here or drop me a message for a confidential chat.
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