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IC Resources

Senior Digital ASIC Design Engineer

West Yorkshire
Posted 1 day ago
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Senior Digital ASIC Design Engineer

A growing semiconductor company is expanding its digital design team and is looking for an experienced engineer to work on the development of complex ASIC technology.

This is an opportunity to join a technically ambitious engineering team and contribute across the digital ASIC development flow, from architecture and RTL design through to tapeout and silicon bring up.

The Role Will Involve

  • Developing synthesizable RTL for control logic, data paths, configuration and high performance digital blocks
  • Defining and integrating digital architectures, including clocking, resets, registers and block level interfaces
  • Working with high speed interfaces and protocols such as PCIe, CXL, UCIe, AXI or AMBA
  • Integrating digital logic with memory, analogue and external interfaces
  • Supporting RTL sign off through lint, CDC, RDC, synthesis, timing and formal analysis
  • Working closely with verification and physical design teams to ensure designs are robust and ready for implementation
  • Supporting FPGA prototyping, tapeout, silicon bring up and hardware debug
  • Contributing to design reviews and helping solve complex technical challenges across the wider engineering team

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I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?

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Graduate Consultant — 2026 Scheme

PwC·London, UK
£35,000/yr

Why you're a good match

Strong

Your economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.

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Why you're a good match

You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.

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Strong

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Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.

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Required Experience

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  • Strong digital ASIC / RTL design experience
  • Advanced SystemVerilog or Verilog
  • Experience through the ASIC flow to tapeout
  • Digital top level integration experience
  • Good understanding of synthesis, timing and CDC
  • Experience working with cross functional engineering teams
  • Degree in Electronics, Computer Engineering or a related subject

For more information on this role or others please contact Jordan Browne at IC Resources.

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Location

West Yorkshire, England, United Kingdom

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