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Redline Group - Specialist Recruitment for Technology & Electronics Companies

Senior FPGA Engineer – Compute Architecture & Hardware Acceleration

Oxford
Posted about 17 hours ago
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Senior FPGA Engineer – Compute Architecture & Hardware Acceleration

Excellent opportunity for a Senior FPGA Engineer – Compute Architecture & Hardware Acceleration to join an innovative technology business on a hybrid basis, with time spent at their Oxford site, helping develop next-generation probabilistic computing platforms and advanced hardware acceleration solutions. This role will require expertise in FPGA design, algorithm implementation, and high-speed digital systems development.

Key Responsibilities

  • Translate complex probabilistic algorithms from Python, C++, MATLAB and pseudocode into highly pipelined, resource-efficient FPGA RTL designs
  • Design and implement custom digital logic in VHDL from scratch where vendor IP is unsuitable, introduces latency or creates bottlenecks
  • Architect and integrate high-speed data acquisition pipelines utilising ultra-fast ADCs, PCIe, high-speed Ethernet and transceiver technologies
  • Work closely with hardware engineers, software developers, researchers and ASIC architects to define system architecture and technical solutions
  • Develop robust verification environments, perform hardware bring-up activities and optimise timing, power and resource utilisation across multiple clock domains

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I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?

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Graduate Consultant — 2026 Scheme

PwC·London, UK
£35,000/yr

Why you're a good match

Strong

Your economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.

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Why you're a good match

You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.

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Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.

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Key Skills Required

  • Degree in Electrical Engineering, Computer Engineering or a related discipline
  • Demonstrable experience of FPGA digital design experience developing complex, high-speed digital systems
  • Strong HDL expertise with a proven ability to develop custom RTL from scratch
  • Experience with FPGA SoC platforms, including practical knowledge of processor-side development and PS/PL architectures such as Zynq
  • Proven ability to translate mathematical or algorithmic models into hardware accelerators using fixed-point arithmetic and bit-accurate modelling techniques
  • Strong understanding of timing closure, clock domain crossing (CDC) and advanced digital design principles
  • Experience with Xilinx Vivado, Vitis and TCL scripting toolchains
  • Familiarity with hardware debugging tools including oscilloscopes, logic analysers, JTAG debuggers and signal generators

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This is an opportunity to work at the forefront of probabilistic computing, helping define the hardware architecture for a revolutionary computing platform while collaborating with leading experts and researchers in the field.

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To apply for the Senior FPGA Engineer – Compute Architecture & Hardware Acceleration role (hybrid and Oxford based), please send your CV to mbelmar@redlinegroup.com, or for more information contact Mike Belmar on 01582 878807.

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Skills

FPGA Design
VHDL
RTL Design
Compute Architecture
Hardware Acceleration
Zynq
Xilinx Vivado
Vitis
TCL Scripting
Fixed-point Arithmetic
Timing Closure
Clock Domain Crossing
PCIe
High-speed Ethernet
Digital Logic Design
Hardware Debugging

Location

Oxford, England, United Kingdom

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