MRL Consulting Group | Global Niche Technology Recruitment
Senior FPGA Validation Engineer – High-Speed Digital Systems

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Senior FPGA Validation Engineer – High-Speed Digital Systems - 4 Days onsite
We’re looking for an experienced DDR / FPGA Validation Engineer to join a highly innovative engineering team working on advanced satellite communications and high-speed digital systems. This is an exciting opportunity for an engineer with strong expertise in DDR validation, FPGA development, system bring-up and signal integrity to work on complex, next-generation technology.
Key Responsibilities
- Validate DDR3/DDR4 interfaces, including timing, voltage, frequency and temperature margins
- Develop comprehensive DDR validation plans and perform eye analysis and BER measurements
- Debug memory training, calibration and initialization issues
- Develop and bring up FPGA-based prototypes
- Perform board bring-up, system integration and hardware/software co-validation
- Validate high-speed interfaces including DDR, PCIe and USB
- Conduct signal integrity / power integrity analysis, including jitter, crosstalk, reflections and eye diagrams
- Develop automated validation and regression tools using Python and C/C++
- Support stress, reliability and production-readiness testing
- Work closely with RTL, memory controller, PHY, firmware, PCB and software teams
Reasons to use Rodeo
I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?
Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.
Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.
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Graduate Consultant — 2026 Scheme
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StrongYour economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.
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You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.
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What We’re Looking For
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering or related discipline
- 5–12+ years’ experience in DDR validation, FPGA development or high-speed digital systems
- Strong knowledge of DDR architecture and JEDEC standards
- Hands-on experience with DDR3/DDR4
- Experience with modem or wireless SoCs (4G/5G) is highly desirable
- Knowledge of memory controller architecture and FPGA bring-up
- Strong programming skills in Python and C/C++
- Experience with Git and automated regression frameworks
- Strong debugging and analytical skills
- Experience with high-speed interfaces such as PCIe, USB, Ethernet, MIPI, UFS, UART, SPI or I2C


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Hands-On Experience
- Experience using equipment such as:
- High-bandwidth oscilloscopes
- JTAG debuggers
- BERT
- TDR
- Thermal chambers
You’ll be working at the forefront of satellite communications, advanced digital systems and high-speed electronics, collaborating with multidisciplinary engineering teams on technically challenging projects.
Interested? Apply now or get in touch to discuss the opportunity.
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