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Senior IC Layout Engineer
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This is a new opportunity for a Senior IC Layout Engineer to join our rapidly scaling Semiconductor client based in Cambridge. Hybrid working is available with this role, 3 days a week in the office.
As the Senior IC Layout Engineer, you will own the custom layout and verification of analog circuits, cells, blocks, and IP for multi-Gigabit high speed SerDes up to and beyond 28Gb/s and/or memory IO in advanced semiconductor technology nodes. You will have the opportunity to lead chip layout activities; hence there’s a lot of scope for career progression and satisfaction as you see your work in the final product.
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As the ideal candidate you will be an experienced Analog IC Layout Engineer, ideally a background working on high speed designs, although high-speed is not essential.
Experience is required in some or all of the following;
- Custom analog layout of circuits and blocks for multi-Gigabit serial data-link transceivers or high frequency circuits
- Layout of high-speed or high frequency circuits such as amplifiers, oscillators, phase-locked loops, delay-locked loops, biasing, buffers, regulators, filters, data converters
- Layout approaches and techniques for high-speed circuits, matching constraints, minimisation of parasitics, power grids and ESD requirements
- Modern semiconductor process technologies including 28nm, 14/16nm, 7nm
- EDA tools for design and verification like Cadence Virtuoso, Spectre/HSpice, Calibre/PVS DRC/LVS, parasitics extraction and modelling, EM, and IR drop, ESD, etc
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