MRL Consulting Group | Global Niche Technology Recruitment
Senior Physical Design Engineer
Get notified of more jobs like this · No spam, ever
How your CV stacks up
Upload your CV to see how well it fits this job role
?%
We are recruiting on behalf of our client, a leading organisation in the satellite communications industry, for an experienced Senior Physical Design Engineer to join their multinational Physical Design team.
This is an opportunity to work on state-of-the-art satellite SoCs, including complex digital and analogue modules and next-generation radiation-hardened satellite modems, using leading-edge process technologies and industry-standard EDA tools.
Key Responsibilities
- Deliver physical implementation of complex SoCs, VLSI devices and test chips, integrating custom designs and third-party IP.
- Own block-level timing closure and manufacturing sign-off, including power planning and analysis.
- Develop timing constraints with RTL/Logic Design teams at block and chip level.
- Implement DFT structures and support chip-level integration, simulation and verification.
- Contribute to improving design scripts and tool flows.
- Collaborate with design teams, IP/library suppliers, EDA vendors and external design service providers.
Reasons to use Rodeo
Start with a chat, not a search bar
Grad scheme, placement, apprenticeship? Not sure what you want yet — that's fine. Your agent talks it through with you and turns "I have no idea" into a shortlist.
It searches the market for you
Every day your agent scans the market matching roles against what actually matters to you, not just keywords on a CV.
Only hits
No noise. No "maybe this fits." Just roles with a clear explanation of why they're right — and where to focus when applying.
About You
Get help with your application
Your very own career expert that helps elevate your application to the next level.
- 8+ years' experience as a Physical Design Engineer.
- Bachelor’s degree in Electrical Engineering, Computer Science or a related field.
- Strong experience across the ASIC/COT physical design flow, including synthesis, floor-planning, P&R, CTS, parasitic extraction, STA, timing closure, physical verification, power analysis, formal verification, DFT/DFM and ATPG.
- Experience with deep sub-micron technologies (28nm or below).
- Experience with Cadence or Synopsys EDA tool flows.
- Strong scripting skills using Tcl, Python, Perl or similar.
- Strong analytical and problem-solving abilities.
- Experience working with cross-functional design teams, third-party IP suppliers and external design partners.
“It took my CV and asked me questions relevant to understanding what kind of jobs to suggest for me. Suggestions were almost perfect. Jobs were exactly what I’ve been looking for.”
Jessica, London
Skills
Location