Responsibilities

• Drive physical implementation from RTL handoff through GDSII signoff, including floorplanning, power planning, placement, clock tree synthesis, routing, and timing closure
• Perform and close static timing analysis across PVT corners; resolve timing violations with design and layout teams
• Develop and maintain robust power delivery networks; perform IR-drop and electromigration analysis and drive fixes to closure
• Execute physical verification (DRC, LVS, antenna, ERC) and resolve issues to achieve clean signoff
• Collaborate with analog layout engineers on mixed-signal integration, including floorplan co-optimization and constraint development for sensitive analog/digital boundaries
• Support design-for-test (DFT) insertion, scan chain stitching, and ATPG pattern generation
• Contribute to flow development, methodology improvements, and automation of physical design tasks
• Support silicon bring-up and debug; correlate physical design decisions with lab measurements

Minimum Qualifications

• BS in Electrical or Computer Engineering (or equivalent)
• 4+ years of experience in ASIC/SoC physical design and implementation
• Strong proficiency with Cadence digital implementation tools (Genus, Innovus, Tempus, Conformal, Voltus, Pegasus)
• Solid understanding of static timing analysis, clock domain crossing, and multi-corner multi-mode signoff
• Experience with mature analog process nodes (e.g., 180nm BCD) in addition to advanced digital nodes
• Experience with power analysis (IR-drop, EM) and power intent specification (UPF/CPF)
• Working knowledge of DFT methodologies (scan insertion, compression, ATPG, JTAG/boundary scan)
• Proficiency in scripting for automation and flow development (Tcl, Python, shell)
• Strong problem-solving skills and ability to work independently with minimal supervision
• Good organization; written and verbal communication skills

Preferred Qualifications

• MS in Electrical or Computer Engineering (or equivalent)
• Experience with mixed-signal SoC physical design, including analog/digital co-integration and constraint management
• Experience with advanced process node physical design (deep submicron FinFET technologies)
• Experience with multi-die or system-in-package (SiP) physical design considerations
• Exposure to low-power design techniques (power gating, multi-voltage domains, level shifters)
• Experience with formal equivalence checking across synthesis and place-and-route stages
• Interest in methodology improvements and EDA flow automation

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Export Licensing Review

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Equal Opportunity Employer

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

EEO is the Law: Notice of Applicant Rights Under the Law.

Job Details

• Job Req Type: Experienced
• Required Travel: Yes, 10% of the time
• Shift Type: 1st Shift/Days