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Senior Staff RF/Analogue IC CAD Engineer – Cadence / SKILL / Physical Verification

Farnborough
Posted 1 day ago
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Senior Staff RF/Analogue IC CAD Engineer – Cadence / SKILL / Physical Verification

We are currently partnered with a highly technical semiconductor organisation seeking a Senior Staff RF/Analogue IC CAD Engineer to develop, maintain, and optimise CAD environments, design flows, and methodologies supporting RF and analogue integrated circuit development. The role combines hands-on CAD engineering with technical leadership, cross-functional collaboration, mentoring, and long-term CAD strategy.

Key responsibilities

  • Design, develop, and maintain Cadence-based CAD flows for RF and analogue IC design, including schematic capture, simulation, layout, and verification.
  • Develop and maintain SKILL/SKILL++ scripts and automation within the Cadence Virtuoso environment to improve designer productivity.
  • Manage and support simulation frameworks using Spectre, ADE, Maestro, and AMS.
  • Set up and maintain corner libraries, Monte Carlo analyses, and process variation analyses.
  • Own and maintain physical verification flows including LVS, DRC, PERC, and ERC.
  • Ensure clean sign-off throughout the IC design cycle.
  • Collaborate with foundry partners to integrate and qualify PDK updates and new process nodes.
  • Manage design data and CAD assets using version control systems including Design Sync.

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I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?

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Graduate Consultant — 2026 Scheme

PwC·London, UK
£35,000/yr

Why you're a good match

Strong

Your economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.

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Why you're a good match

You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.

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Strong

Experience fit

Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.

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Key requirements

  • Bachelor’s degree in Science, Engineering, or a related field and 6+ years of ASIC design, verification, validation, integration, or related experience.
  • Alternatively, Master’s degree in Science, Engineering, or a related field and 5+ years of relevant experience.
  • Alternatively, PhD in Science, Engineering, or a related field and 4+ years of relevant experience.
  • Strong experience with Cadence-based RF/analogue CAD environments.
  • Strong experience with physical verification flows.
  • Strong SKILL automation experience.
  • Experience developing and maintaining CAD flows and methodologies.
  • Ability to solve complex CAD and design-flow challenges.
  • Experience supporting design infrastructure across process nodes and technology generations.
  • Ability to provide technical leadership and work effectively with design and project leads.
  • Strong understanding of CAD solution quality and integrity.

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Keywords

Senior Staff RF/Analogue IC CAD Engineer / RF IC / Analogue IC / ASIC / CAD Engineering / CAD Infrastructure / CAD Flows / CAD Methodologies / Cadence / Cadence Virtuoso / SKILL / SKILL++ / Schematic Capture / Simulation / Layout / IC Verification / Spectre / ADE / Maestro / AMS / Corner Libraries / Monte Carlo / Process Variation Analysis / LVS / DRC / PERC / ERC / Physical Verification / Sign-off / PDK / Process Nodes / Foundry / Design Sync / Mentor / Siemens / Version Control / Design Data / CAD Assets / RF / Analogue / Mixed Signal / Backend Flows / Extraction / Post-Layout Simulation / Regression Frameworks / Python / Data Analysis / Automation / Git / Perforce / Momentum / EMX / HFSS / Technical Leadership / CAD Strategy / IC Design / Design Reviews

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Location

Farnborough, England, United Kingdom

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