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Senior Validation Engineer

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Senior Validation Engineer – Analog/Mixed-Signal – Edinburgh
A leading semiconductor company is seeking a Senior Validation Engineer to join its Validation Engineering team and play a key role in bringing next-generation mixed-signal products to market. This is a hands-on position spanning pre-silicon emulation, post-silicon validation, board bring-up, automated testing, and silicon debug.
What you'll do as a Senior Validation Engineer:
- Develop and execute bench-level validation tests across pre-silicon and post-silicon phases
- Validate mixed-signal ICs against functionality and performance requirements
- Perform hands-on testing and debugging of embedded circuitry including amplifiers, data converters, and power converters
- Design, develop, and debug silicon validation boards and bring-up platforms ahead of first silicon
- Develop automated validation frameworks and regression test suites using Python
- Analyse validation data to identify failures, defects, and performance issues
Reasons to use Rodeo
I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?
Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.
Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.
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Graduate Consultant — 2026 Scheme
Why you're a good match
StrongYour economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.
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Every day your agent scans the market matching roles against what actually matters to you, not just keywords on a CV.
Why you're a good match
You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.
Experience fit
Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.
Only hits
No noise. No "maybe this fits." Just roles with a clear explanation of why they're right — and where to focus when applying.
What you'll bring as a Senior Validation Engineer:
- Analog or Digital chip validation experience
- Strong understanding of mixed-signal blocks such as ADCs, DACs, PLLs
- Experience understanding interactions between silicon, PCB hardware, and software
- Experience developing automated test solutions using Python or other scripting languages
- Experience in post-silicon validation or mixed-signal IP validation
- Experience with interfaces such as I2C, SPI, USB, I2S, and TDM


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If you would like to apply for the Senior Validation Engineer vacancy or would like further information, please contact Luke Ord.
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