IC Resources
Senior Verification Engineer

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About the Opportunity
This is a fantastic opportunity to join a start-up who are a couple of years old, as they make technological breakthroughs in security with a product line built on CHERI technology and RISC-V cores.
About the Role
I am looking for Verification Engineers between 8-16 years experience to join a talented team. You will work in an environment where you are not pigeon holed to one or two tasks but have the scope and autonomy to work on complex tasks across the whole flow.
The company have strong funding behind them and a leadership team made up of experts in processor design and formal methods as well as a CEO who brings over 30 years of semiconductor experience from world renown companies and start-ups.
Reasons to use Rodeo
I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?
Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.
Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.
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Graduate Consultant — 2026 Scheme
Why you're a good match
StrongYour economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.
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Why you're a good match
You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.
Experience fit
Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.
Only hits
No noise. No "maybe this fits." Just roles with a clear explanation of why they're right — and where to focus when applying.
Responsibilities
- Collaborates with the design team to understand and define verification requirements for security features
- Develops and maintains verification plans, testbenches, and test scenarios using UVM methodology
- Executes test plans and verifies the correctness of hardware security features
- Works closely with the cross-functional teams to ensure the implementation meets design specifications and security requirements
- Identifies and debugs issues found during verification and works to resolve them in a timely manner
Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
- Strong understanding of hardware verification methodologies and tools
- Experience with UVM (Universal Verification Methodology) for FPGA/ASIC verification
- Familiarity with security features and protocols, such as CHERI, is a plus
- Excellent communication skills and the ability to work effectively in a collaborative, multidisciplinary team
- Knowledge of UK working rights


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Location
Cambridge, Sheffield or UK Remote: You must be currently living and working in the UK and able to do so without restrictions.
You must have UK working rights to be considered for the role.
For more details, please contact Rachel Mason.
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