IC Resources
Senior Verification Engineer

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Join a world-class semiconductor powerhouse in Edinburgh, one of Europe’s most attractive tech hubs. Known for its thriving semiconductor ecosystem, outstanding quality of life, and easy access to nature, Edinburgh offers the perfect balance between cutting-edge engineering work and lifestyle. This role provides an opportunity for experienced verification engineers to make a long-term move to the UK.
In this role, you’ll be responsible for ensuring the functional correctness and robustness of complex digital and mixed-signal ASIC designs using advanced verification methodologies.
Key Responsibilities
- Develop and execute comprehensive verification plans for complex mixed-signal ASIC designs
- Create and maintain UVM-based SystemVerilog testbenches
- Write, debug, and execute test cases to verify functionality, performance, and corner cases
- Perform block-level and full-chip verification, including simulation, coverage analysis, and regression management
- Collaborate closely with design engineers to interpret specifications and define verification requirements
- Analyse and resolve issues discovered during verification and post-silicon validation
- Mentor junior engineers and drive improvements in verification methodologies and infrastructure
- Participate in code reviews and contribute to continuous improvement of design and verification best practices
Reasons to use Rodeo
I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?
Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.
Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.
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Graduate Consultant — 2026 Scheme
Why you're a good match
StrongYour economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.
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Why you're a good match
You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.
Experience fit
Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.
Only hits
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Qualifications
- 5+ years’ experience in digital and/or mixed-signal design verification
- Strong proficiency in SystemVerilog, UVM, and leading simulation tools (e.g., Synopsys VCS, Cadence Xcelium)
- Solid understanding of digital design principles, RTL design, and ASIC development flows
- Experience with scripting languages (Python, Perl, Shell, etc.)
- Familiarity with formal verification, assertion-based verification, and coverage-driven verification techniques
- Excellent problem-solving skills and attention to detail


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What’s On Offer
- Competitive base salary plus RSUs and annual bonus
- A collaborative, innovative working environment
For more information on this role or others then please contact Jordan Browne for more information.
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