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Senior/Staff CPU Physical Design Engineer - High-Performance Compute / Semiconductors

Cambridge
Posted about 13 hours ago
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Senior/Staff CPU Physical Design Engineer - High-Performance Compute / Semiconductors

We are partnered with a global leader in semiconductor and wireless technology innovation. The team is looking to hire a Senior or Staff Server CPU Physical Design Engineer to own block-level physical implementation for next-generation, high-performance custom CPU cores targeting advanced compute and server-class platforms.

This is a permanent, fully onsite opportunity based in Cambridge, UK.

Key responsibilities

  • Own or contribute to CPU block implementation from RTL/netlist to GDS
  • Drive timing closure and physical implementation convergence across multiple modes, corners, and operating conditions.
  • Debug and resolve complex implementation issues across timing, congestion, clocking, IR drop, power integrity, EM, and DRC/LVS.
  • Collaborate with RTL, architecture, circuits, CAD, SoC, and post-silicon teams to improve design quality and PPA.
  • Develop and enhance physical design flows, automation, and methodologies.

Reasons to use Rodeo

I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?

Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.

Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.

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Graduate Consultant — 2026 Scheme

PwC·London, UK
£35,000/yr

Why you're a good match

Strong

Your economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.

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Why you're a good match

You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.

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Strong

Experience fit

Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.

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Strong

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Key requirements

  • Strong experience in physical design — synthesis, floorplanning, placement, CTS, routing, timing closure, ECOs, and signoff.
  • Solid understanding of STA and timing closure methodologies, including PPA trade-offs.
  • Hands-on experience with industry-standard EDA tools — Genus, Innovus, Fusion Compiler, PrimeTime, Tempus, Voltus, RedHawk, or equivalent.
  • Scripting experience in TCL, Python, or Perl.
  • Experience on CPU cores, advanced nodes (7nm and below), or low-power design techniques advantageous.

Keywords

Server CPU Physical Design Engineer / Physical Design / Place & Route / Floorplanning / CTS / Timing Closure / STA / ECO / Synthesis / Innovus / Fusion Compiler / PrimeTime / Tempus / Voltus / RedHawk / DRC / LVS / Low Power / CPU / High Performance Compute / Advanced Nodes / TCL / Python

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If you are interested in this Server CPU Physical Design Engineer position, please send a copy of your CV to ts@eu-recruit.com

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Skills

Physical Design
Synthesis
Floorplanning
Placement
CTS
Routing
Timing Closure
STA
ECOs
Genus
Innovus
Fusion Compiler
PrimeTime
Tempus
Voltus
RedHawk

Location

Cambridge, England, United Kingdom

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