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SOC Architect / ASIC Architect – RF Systems

City of Edinburgh
£100k/yr
Posted about 17 hours ago
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Brand new, and cutting edge project, working for an exciting scale-up in the semiconductor space – to be based full-time from Scotland.

Salary Is Circa £100k (Plus Amazing Additional Package)

I am looking for a SOC Architect / ASIC Architect to be responsible for the definition of high-level architecture for new chips + the development of existing ones, definition of the whole process & design flow and guidance on RTL design of new chips.

Must Have Experience

  • Degree / Masters / PhD in electronics / micro-electronics, physics or similar field
  • 10-20 years’ experience of full chip design and delivery / as a chip lead / or SOC architect
  • Digital / AMS, analog-mixed-signal IP
  • End to end chip / SOC delivery experience
  • ASIC & FPGA – verilog, system verilog, VHDL
  • ADC / DAC – digital – analog interfaces
  • Detailed knowledge of complex tape-out processes, and interactions with fabrication plants
  • Full digital design flow, from RTL2GDS
  • SOC design, integration, system design, system architecture
  • Chip experience from any of the following areas (or similar) – power management / PMIC / ultra-low power / optimisation & performance

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I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?

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Graduate Consultant — 2026 Scheme

PwC·London, UK
£35,000/yr

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Your economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.

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Why you're a good match

You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.

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Bonus / Nice To Have Skills

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  • Complex cores / processors / CPUs etc.
  • NOC interconnects
  • PLLs / filter design
  • RF-SOC / RF System architecture
  • DSP, signal processing
  • Flash memory – DDR / HBM / high-bandwidth memory / cache coherency
  • clock, timing constraints

This position is ONLY available to engineers with full UK working rights

Please contact Rob Hudson for more information.

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Skills

SOC Architecture
ASIC Design
RTL Design
Verilog
System Verilog
VHDL
Analog-Mixed-Signal IP
Tape-out Processes
RTL2GDS Flow
FPGA
ADC/DAC Interfaces
Power Management
RF System Architecture
DSP
NOC Interconnects
PLL Design

Location

City of Edinburgh, Scotland, United Kingdom

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