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SOC Design Lead / SOC Architect

Scotland
£100k/yr
Posted about 16 hours ago
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Brand new, and cutting edge project, working for an exciting scale-up in the semiconductor space - to be based full-time from Scotland.

Salary is circa £100k (PLUS AMAZING ADDITIONAL PACKAGE)

I am looking for a SOC Chip Design Lead / SOC Architect to be responsible for the end to end design, set-up, architecture definition, definition of the whole process & design flow and RTL design of new chips.

You will be the lead designer / architect with end to end responsibility for delivering the full chip to delivery at the fab.

Must have experience:

  • Degree / Masters / PhD in electronics / micro-electronics, physics or similar field
  • 10-20 years' experience of full chip design and delivery / as a chip lead / or SOC architect
  • Digital / AMS, analog-mixed-signal IP
  • End to end chip / SOC delivery experience
  • ASIC & FPGA - verilog, system verilog, VHDL
  • ADC / DAC - digital - analog interfaces
  • Functional verification - system verilog - IP, system, sub-system, block, top level experience
  • Creation of test-benches
  • Detailed knowledge of complex tape-out processes, and interactions with fabrication plants
  • Full digital design flow, from RTL2GDS
  • SOC design, integration, system design, system architecture
  • Power management / PMIC / ultra-low power / optimisation & performance
  • Synthesis / HLS / STA
  • Physical implementation / physical design

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Graduate Consultant — 2026 Scheme

PwC·London, UK
£35,000/yr

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Your economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.

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You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.

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Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.

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  • Complex cores / processors / CPUs etc.
  • PLLs / filter design
  • RF-SOC
  • DSP, signal processing
  • Flash memory - DDR / HBM / high-bandwidth memory / cache chorency
  • Clock, timing constraints

This position is ONLY available to engineers with full UK working rights

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Skills

SOC Architecture
RTL Design
ASIC
FPGA
Verilog
System Verilog
VHDL
Analog-Mixed-Signal IP
Functional Verification
Tape-out Process
RTL2GDS
Power Management
Synthesis
STA
Physical Design
HLS

Location

Scotland, United Kingdom

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