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Staff RTL/Digital Design Engineer - (CPU Team) - Visas Transfers Supported

Cambridge
Posted 1 day ago
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CPU RTL Design Engineer (Staff)

A fantastic opportunity for an experienced RTL Design Engineer to join a global leader in semiconductors, working alongside their CPU Team in Cambridge (UK).

About the Role

Working on CPU RTL development targeted for high performance, low power devices, as a CPU Micro-architecture and RTL Design Engineer, you will work with chip architects to conceive of the micro-architecture, and also help with architecture/product definition through early involvement in the product life-cycle.

What will you be doing?

  • Performance exploration. Explore high performance strategies working with the CPU modelling team.
  • Microarchitecture development and specification. From early high-level architectural exploration, through micro architectural research and arriving at a detailed specification.
  • RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing goals.
  • Functional verification support. Help the design verification team execute on the functional verification strategy.
  • Performance verification support. Help verify that the RTL design meets the performance goals.
  • Design delivery. Work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and power.

Reasons to use Rodeo

I’m in my final year doing Economics and I don’t know whether to apply for grad schemes now or do a masters first. What do you think?

Honest answer — it depends on where you want to end up. A lot of top grad schemes (Big 4, civil service, banking) don’t need a masters. Let’s look at the ones you’d be competitive for now, and we can decide if a masters actually adds anything.

Also worth knowing: most autumn 2026 applications are open now. Timing matters more than you think.

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Grad scheme, placement, apprenticeship? Not sure what you want yet — that's fine. Your agent talks it through with you and turns "I have no idea" into a shortlist.

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Graduate Consultant — 2026 Scheme

PwC·London, UK
£35,000/yr

Why you're a good match

Strong

Your economics background and your summer at a regional bank line up with what PwC looks for on the consulting scheme. Applications close in four weeks.

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Why you're a good match

You’ve got the grades and the economics background, and your bank internship is exactly the experience this scheme looks for. Apply soon — deadlines close within the month.

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Strong

Experience fit

Your summer at the bank plus your econometrics coursework map directly to the day-one responsibilities on this scheme — client modelling, market briefings, and deal support.

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Only hits

No noise. No "maybe this fits." Just roles with a clear explanation of why they're right — and where to focus when applying.

What are we looking for?

  • Thorough knowledge of microprocessor architecture including expertise in one or more of the following areas: instruction fetch and decode, branch prediction, instruction scheduling and register renaming, out-of-order execution, integer and floating point execution, load/store execution, prefetching, cache and memory subsystems
  • Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools
  • Knowledge of logic design principles along with timing and power implications
  • Understanding of low power microarchitecture techniques
  • Understanding of high performance techniques and trade-offs in a CPU microarchitecture
  • Experience using a scripting language such as Perl or Python

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Skills

RTL Design
CPU Micro-architecture
Verilog
VHDL
Microprocessor Architecture
Logic Design
Low Power Design
Performance Verification
Python
Perl
Waveform Debugging
Instruction Scheduling
Cache and Memory Subsystems
Out-of-order Execution
Branch Prediction
Functional Verification

Location

Cambridge, England, United Kingdom

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